1257 lines
94 KiB
C
Executable File
1257 lines
94 KiB
C
Executable File
// This file was generated by the create_regs script
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#define HDMI_BASE 0x7e902000
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#define HDMI_CORE_REV HW_REGISTER_RW( 0x7e902000 )
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#define HDMI_CORE_REV_MASK 0x0000ffff
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#define HDMI_CORE_REV_WIDTH 16
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#define HDMI_CORE_REV_RESET 0x00000600
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#define HDMI_SW_RESET_CNTRL HW_REGISTER_RW( 0x7e902004 )
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#define HDMI_SW_RESET_CNTRL_MASK 0x00000003
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#define HDMI_SW_RESET_CNTRL_WIDTH 2
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#define HDMI_SW_RESET_CNTRL_RESET 0000000000
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#define HDMI_HOTPLUG_INT HW_REGISTER_RW( 0x7e902008 )
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#define HDMI_HOTPLUG_INT_MASK 0x00000007
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#define HDMI_HOTPLUG_INT_WIDTH 3
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#define HDMI_HOTPLUG_INT_RESET 0x00000006
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#define HDMI_HOTPLUG HW_REGISTER_RW( 0x7e90200c )
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#define HDMI_HOTPLUG_MASK 0x00000001
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#define HDMI_HOTPLUG_WIDTH 1
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#define HDMI_HOTPLUG_RESET 0000000000
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#define HDMI_BKSV0 HW_REGISTER_RW( 0x7e902010 )
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#define HDMI_BKSV0_MASK 0xffffffff
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#define HDMI_BKSV0_WIDTH 32
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#define HDMI_BKSV0_RESET 0000000000
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#define HDMI_BKSV1 HW_REGISTER_RW( 0x7e902014 )
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#define HDMI_BKSV1_MASK 0xffffffff
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#define HDMI_BKSV1_WIDTH 32
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#define HDMI_BKSV1_RESET 0000000000
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#define HDMI_AN0 HW_REGISTER_RW( 0x7e902018 )
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#define HDMI_AN0_MASK 0xffffffff
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#define HDMI_AN0_WIDTH 32
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#define HDMI_AN0_RESET 0000000000
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#define HDMI_AN1 HW_REGISTER_RW( 0x7e90201c )
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#define HDMI_AN1_MASK 0xffffffff
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#define HDMI_AN1_WIDTH 32
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#define HDMI_AN1_RESET 0000000000
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#define HDMI_AN_INFLUENCE_1 HW_REGISTER_RW( 0x7e902020 )
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#define HDMI_AN_INFLUENCE_1_MASK 0xffffffff
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#define HDMI_AN_INFLUENCE_1_WIDTH 32
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#define HDMI_AN_INFLUENCE_1_RESET 0000000000
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#define HDMI_AN_INFLUENCE_2 HW_REGISTER_RW( 0x7e902024 )
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#define HDMI_AN_INFLUENCE_2_MASK 0xffffffff
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#define HDMI_AN_INFLUENCE_2_WIDTH 32
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#define HDMI_AN_INFLUENCE_2_RESET 0000000000
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#define HDMI_TST_AN0 HW_REGISTER_RW( 0x7e902028 )
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#define HDMI_TST_AN0_MASK 0xffffffff
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#define HDMI_TST_AN0_WIDTH 32
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#define HDMI_TST_AN0_RESET 0000000000
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#define HDMI_TST_AN1 HW_REGISTER_RW( 0x7e90202c )
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#define HDMI_TST_AN1_MASK 0xffffffff
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#define HDMI_TST_AN1_WIDTH 32
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#define HDMI_TST_AN1_RESET 0000000000
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#define HDMI_KSV_FIFO_0 HW_REGISTER_RW( 0x7e902030 )
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#define HDMI_KSV_FIFO_0_MASK 0xffffffff
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#define HDMI_KSV_FIFO_0_WIDTH 32
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#define HDMI_KSV_FIFO_0_RESET 0000000000
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#define HDMI_KSV_FIFO_1 HW_REGISTER_RW( 0x7e902034 )
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#define HDMI_KSV_FIFO_1_MASK 0x000000ff
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#define HDMI_KSV_FIFO_1_WIDTH 8
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#define HDMI_KSV_FIFO_1_RESET 0000000000
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#define HDMI_V HW_REGISTER_RW( 0x7e902038 )
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#define HDMI_V_MASK 0xffffffff
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#define HDMI_V_WIDTH 32
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#define HDMI_V_RESET 0000000000
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#define HDMI_HDCP_KEY_1 HW_REGISTER_RW( 0x7e90203c )
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#define HDMI_HDCP_KEY_1_MASK 0xffffff3f
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#define HDMI_HDCP_KEY_1_WIDTH 32
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#define HDMI_HDCP_KEY_1_RESET 0000000000
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#define HDMI_HDCP_KEY_2 HW_REGISTER_RW( 0x7e902040 )
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#define HDMI_HDCP_KEY_2_MASK 0xffffffff
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#define HDMI_HDCP_KEY_2_WIDTH 32
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#define HDMI_HDCP_KEY_2_RESET 0000000000
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#define HDMI_HDCP_CTL HW_REGISTER_RW( 0x7e902044 )
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#define HDMI_HDCP_CTL_MASK 0x0001030f
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#define HDMI_HDCP_CTL_WIDTH 17
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#define HDMI_HDCP_CTL_RESET 0000000000
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#define HDMI_CP_STATUS HW_REGISTER_RW( 0x7e902048 )
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#define HDMI_CP_STATUS_MASK 0x8000031f
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#define HDMI_CP_STATUS_WIDTH 32
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#define HDMI_CP_STATUS_RESET 0x00000100
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#define HDMI_CP_INTEGRITY HW_REGISTER_RW( 0x7e90204c )
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#define HDMI_CP_INTEGRITY_MASK 0xffffff03
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#define HDMI_CP_INTEGRITY_WIDTH 32
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#define HDMI_CP_INTEGRITY_RESET 0000000000
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#define HDMI_CP_INTEGRITY_CFG HW_REGISTER_RW( 0x7e902050 )
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#define HDMI_CP_INTEGRITY_CFG_MASK 0x0001ffff
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#define HDMI_CP_INTEGRITY_CFG_WIDTH 17
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#define HDMI_CP_INTEGRITY_CFG_RESET 0x00001000
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#define HDMI_CP_CONFIG HW_REGISTER_RW( 0x7e902054 )
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#define HDMI_CP_CONFIG_MASK 0x7fffffff
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#define HDMI_CP_CONFIG_WIDTH 31
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#define HDMI_CP_CONFIG_RESET 0x00130080
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#define HDMI_CP_TST HW_REGISTER_RW( 0x7e902058 )
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#define HDMI_CP_TST_MASK 0x002001ff
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#define HDMI_CP_TST_WIDTH 22
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#define HDMI_CP_TST_RESET 0000000000
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#define HDMI_FIFO_CTL HW_REGISTER_RW( 0x7e90205c )
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#define HDMI_FIFO_CTL_MASK 0x0000efff
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#define HDMI_FIFO_CTL_WIDTH 16
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#define HDMI_FIFO_CTL_RESET 0000000000
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#define HDMI_FIFO_CTL_ON_VB_DONE_BITS 15:15
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#define HDMI_FIFO_CTL_ON_VB_DONE_SET 0x00008000
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#define HDMI_FIFO_CTL_ON_VB_DONE_CLR 0xffff7fff
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#define HDMI_FIFO_CTL_ON_VB_DONE_MSB 15
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#define HDMI_FIFO_CTL_ON_VB_DONE_LSB 15
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#define HDMI_FIFO_CTL_RECENTER_DONE_BITS 14:14
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#define HDMI_FIFO_CTL_RECENTER_DONE_SET 0x00004000
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#define HDMI_FIFO_CTL_RECENTER_DONE_CLR 0xffffbfff
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#define HDMI_FIFO_CTL_RECENTER_DONE_MSB 14
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#define HDMI_FIFO_CTL_RECENTER_DONE_LSB 14
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#define HDMI_FIFO_CTL_USE_EMPTY_BITS 13:13
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#define HDMI_FIFO_CTL_USE_EMPTY_SET 0x00002000
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#define HDMI_FIFO_CTL_USE_EMPTY_CLR 0xffffdfff
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#define HDMI_FIFO_CTL_USE_EMPTY_MSB 13
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#define HDMI_FIFO_CTL_USE_EMPTY_LSB 13
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#define HDMI_FIFO_CTL_VB_CNT_BITS 11:8
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#define HDMI_FIFO_CTL_VB_CNT_SET 0x00000f00
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#define HDMI_FIFO_CTL_VB_CNT_CLR 0xfffff0ff
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#define HDMI_FIFO_CTL_VB_CNT_MSB 11
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#define HDMI_FIFO_CTL_VB_CNT_LSB 8
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#define HDMI_FIFO_CTL_ON_VB_BITS 7:7
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#define HDMI_FIFO_CTL_ON_VB_SET 0x00000080
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#define HDMI_FIFO_CTL_ON_VB_CLR 0xffffff7f
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#define HDMI_FIFO_CTL_ON_VB_MSB 7
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#define HDMI_FIFO_CTL_ON_VB_LSB 7
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#define HDMI_FIFO_CTL_RECENTER_BITS 6:6
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#define HDMI_FIFO_CTL_RECENTER_SET 0x00000040
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#define HDMI_FIFO_CTL_RECENTER_CLR 0xffffffbf
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#define HDMI_FIFO_CTL_RECENTER_MSB 6
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#define HDMI_FIFO_CTL_RECENTER_LSB 6
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#define HDMI_FIFO_CTL_FIFO_RESET_BITS 5:5
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#define HDMI_FIFO_CTL_FIFO_RESET_SET 0x00000020
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#define HDMI_FIFO_CTL_FIFO_RESET_CLR 0xffffffdf
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#define HDMI_FIFO_CTL_FIFO_RESET_MSB 5
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#define HDMI_FIFO_CTL_FIFO_RESET_LSB 5
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#define HDMI_FIFO_CTL_USE_PLL_LOCK_BITS 4:4
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#define HDMI_FIFO_CTL_USE_PLL_LOCK_SET 0x00000010
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#define HDMI_FIFO_CTL_USE_PLL_LOCK_CLR 0xffffffef
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#define HDMI_FIFO_CTL_USE_PLL_LOCK_MSB 4
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#define HDMI_FIFO_CTL_USE_PLL_LOCK_LSB 4
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#define HDMI_FIFO_CTL_INV_CLK_XFR_BITS 3:3
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#define HDMI_FIFO_CTL_INV_CLK_XFR_SET 0x00000008
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#define HDMI_FIFO_CTL_INV_CLK_XFR_CLR 0xfffffff7
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#define HDMI_FIFO_CTL_INV_CLK_XFR_MSB 3
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#define HDMI_FIFO_CTL_INV_CLK_XFR_LSB 3
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#define HDMI_FIFO_CTL_CAPTURE_POINTER_BITS 2:2
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#define HDMI_FIFO_CTL_CAPTURE_POINTER_SET 0x00000004
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#define HDMI_FIFO_CTL_CAPTURE_POINTER_CLR 0xfffffffb
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#define HDMI_FIFO_CTL_CAPTURE_POINTER_MSB 2
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#define HDMI_FIFO_CTL_CAPTURE_POINTER_LSB 2
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#define HDMI_FIFO_CTL_USE_FULL_BITS 1:1
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#define HDMI_FIFO_CTL_USE_FULL_SET 0x00000002
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#define HDMI_FIFO_CTL_USE_FULL_CLR 0xfffffffd
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#define HDMI_FIFO_CTL_USE_FULL_MSB 1
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#define HDMI_FIFO_CTL_USE_FULL_LSB 1
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#define HDMI_FIFO_CTL_MASTER_SLAVE_N_BITS 0:0
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#define HDMI_FIFO_CTL_MASTER_SLAVE_N_SET 0x00000001
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#define HDMI_FIFO_CTL_MASTER_SLAVE_N_CLR 0xfffffffe
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#define HDMI_FIFO_CTL_MASTER_SLAVE_N_MSB 0
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#define HDMI_FIFO_CTL_MASTER_SLAVE_N_LSB 0
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#define HDMI_READ_POINTERS HW_REGISTER_RW( 0x7e902060 )
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#define HDMI_READ_POINTERS_MASK 0x7fffffff
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#define HDMI_READ_POINTERS_WIDTH 31
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#define HDMI_READ_POINTERS_RESET 0000000000
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#define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_BITS 30:30
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#define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_SET 0x40000000
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#define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_CLR 0xbfffffff
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#define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_MSB 30
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#define HDMI_READ_POINTERS_DOMAIN_HALF_FULL_LSB 30
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#define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_BITS 29:27
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#define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_SET 0x38000000
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#define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_CLR 0xc7ffffff
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#define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_MSB 29
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#define HDMI_READ_POINTERS_DOMAIN_WR_ADDR_LSB 27
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#define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_BITS 26:24
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#define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_SET 0x07000000
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#define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_CLR 0xf8ffffff
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#define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_MSB 26
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#define HDMI_READ_POINTERS_DOMAIN_RESYNC_RD_LSB 24
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#define HDMI_READ_POINTERS_DRFT_HOLD_WR_BITS 23:23
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#define HDMI_READ_POINTERS_DRFT_HOLD_WR_SET 0x00800000
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#define HDMI_READ_POINTERS_DRFT_HOLD_WR_CLR 0xff7fffff
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#define HDMI_READ_POINTERS_DRFT_HOLD_WR_MSB 23
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#define HDMI_READ_POINTERS_DRFT_HOLD_WR_LSB 23
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#define HDMI_READ_POINTERS_DRFT_HOLD_RD_BITS 22:22
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#define HDMI_READ_POINTERS_DRFT_HOLD_RD_SET 0x00400000
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#define HDMI_READ_POINTERS_DRFT_HOLD_RD_CLR 0xffbfffff
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#define HDMI_READ_POINTERS_DRFT_HOLD_RD_MSB 22
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#define HDMI_READ_POINTERS_DRFT_HOLD_RD_LSB 22
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#define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_BITS 21:21
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#define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_SET 0x00200000
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#define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_CLR 0xffdfffff
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#define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_MSB 21
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#define HDMI_READ_POINTERS_DRFT_ALMOST_FULL_LSB 21
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#define HDMI_READ_POINTERS_DRFT_FULL_MINUS_BITS 20:20
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#define HDMI_READ_POINTERS_DRFT_FULL_MINUS_SET 0x00100000
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#define HDMI_READ_POINTERS_DRFT_FULL_MINUS_CLR 0xffefffff
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#define HDMI_READ_POINTERS_DRFT_FULL_MINUS_MSB 20
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#define HDMI_READ_POINTERS_DRFT_FULL_MINUS_LSB 20
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#define HDMI_READ_POINTERS_DRFT_OVERFLOW_BITS 19:19
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#define HDMI_READ_POINTERS_DRFT_OVERFLOW_SET 0x00080000
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#define HDMI_READ_POINTERS_DRFT_OVERFLOW_CLR 0xfff7ffff
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#define HDMI_READ_POINTERS_DRFT_OVERFLOW_MSB 19
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#define HDMI_READ_POINTERS_DRFT_OVERFLOW_LSB 19
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#define HDMI_READ_POINTERS_DRFT_ALMOST_MT_BITS 18:18
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#define HDMI_READ_POINTERS_DRFT_ALMOST_MT_SET 0x00040000
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#define HDMI_READ_POINTERS_DRFT_ALMOST_MT_CLR 0xfffbffff
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#define HDMI_READ_POINTERS_DRFT_ALMOST_MT_MSB 18
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#define HDMI_READ_POINTERS_DRFT_ALMOST_MT_LSB 18
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#define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_BITS 17:17
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#define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_SET 0x00020000
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#define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_CLR 0xfffdffff
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#define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_MSB 17
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#define HDMI_READ_POINTERS_DRFT_EMPTY_MINUS_LSB 17
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#define HDMI_READ_POINTERS_DRFT_UNDERFLOW_BITS 16:16
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#define HDMI_READ_POINTERS_DRFT_UNDERFLOW_SET 0x00010000
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#define HDMI_READ_POINTERS_DRFT_UNDERFLOW_CLR 0xfffeffff
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#define HDMI_READ_POINTERS_DRFT_UNDERFLOW_MSB 16
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#define HDMI_READ_POINTERS_DRFT_UNDERFLOW_LSB 16
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#define HDMI_READ_POINTERS_DRFT_WR_ADDR_BITS 15:8
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#define HDMI_READ_POINTERS_DRFT_WR_ADDR_SET 0x0000ff00
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#define HDMI_READ_POINTERS_DRFT_WR_ADDR_CLR 0xffff00ff
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#define HDMI_READ_POINTERS_DRFT_WR_ADDR_MSB 15
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#define HDMI_READ_POINTERS_DRFT_WR_ADDR_LSB 8
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#define HDMI_READ_POINTERS_DRFT_RD_ADDR_BITS 7:7
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#define HDMI_READ_POINTERS_DRFT_RD_ADDR_SET 0x00000080
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#define HDMI_READ_POINTERS_DRFT_RD_ADDR_CLR 0xffffff7f
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#define HDMI_READ_POINTERS_DRFT_RD_ADDR_MSB 7
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#define HDMI_READ_POINTERS_DRFT_RD_ADDR_LSB 7
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#define HDMI_ENCODER_CTL HW_REGISTER_RW( 0x7e902070 )
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#define HDMI_ENCODER_CTL_MASK 0x00000001
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#define HDMI_ENCODER_CTL_WIDTH 1
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#define HDMI_ENCODER_CTL_RESET 0000000000
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#define HDMI_PERT_CONFIG HW_REGISTER_RW( 0x7e902074 )
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#define HDMI_PERT_CONFIG_MASK 0x00000fff
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#define HDMI_PERT_CONFIG_WIDTH 12
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#define HDMI_PERT_CONFIG_RESET 0000000000
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#define HDMI_PERT_LFSR_PRELOAD HW_REGISTER_RW( 0x7e902078 )
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#define HDMI_PERT_LFSR_PRELOAD_MASK 0xffffffff
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#define HDMI_PERT_LFSR_PRELOAD_WIDTH 32
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#define HDMI_PERT_LFSR_PRELOAD_RESET 0000000000
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#define HDMI_PERT_LFSR_FEEDBACK_MASK HW_REGISTER_RW( 0x7e90207c )
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#define HDMI_PERT_LFSR_FEEDBACK_MASK_MASK 0xffffffff
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#define HDMI_PERT_LFSR_FEEDBACK_MASK_WIDTH 32
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#define HDMI_PERT_LFSR_FEEDBACK_MASK_RESET 0000000000
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#define HDMI_PERT_INSERT_ERR HW_REGISTER_RW( 0x7e902080 )
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#define HDMI_PERT_INSERT_ERR_MASK 0x00ffffff
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#define HDMI_PERT_INSERT_ERR_WIDTH 24
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#define HDMI_PERT_INSERT_ERR_RESET 0000000000
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#define HDMI_PERT_INSERT_ERR_SEP HW_REGISTER_RW( 0x7e902084 )
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#define HDMI_PERT_INSERT_ERR_SEP_MASK 0xffffffff
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#define HDMI_PERT_INSERT_ERR_SEP_WIDTH 32
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#define HDMI_PERT_INSERT_ERR_SEP_RESET 0000000000
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#define HDMI_PERT_TEST_LENGTH HW_REGISTER_RW( 0x7e902088 )
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#define HDMI_PERT_TEST_LENGTH_MASK 0xffffffff
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#define HDMI_PERT_TEST_LENGTH_WIDTH 32
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#define HDMI_PERT_TEST_LENGTH_RESET 0000000000
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#define HDMI_PERT_DATA HW_REGISTER_RW( 0x7e90208c )
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#define HDMI_PERT_DATA_MASK 0x00ffffff
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#define HDMI_PERT_DATA_WIDTH 24
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#define HDMI_PERT_DATA_RESET 0000000000
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#define HDMI_MAI_CHANNEL_MAP HW_REGISTER_RW( 0x7e902090 )
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#define HDMI_MAI_CHANNEL_MAP_MASK 0x00ffffff
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#define HDMI_MAI_CHANNEL_MAP_WIDTH 24
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#define HDMI_MAI_CHANNEL_MAP_RESET 0x00fac688
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#define HDMI_MAI_CONFIG HW_REGISTER_RW( 0x7e902094 )
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#define HDMI_MAI_CONFIG_MASK 0x0fffffff
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#define HDMI_MAI_CONFIG_WIDTH 28
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#define HDMI_MAI_CONFIG_RESET 0x00000003
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#define HDMI_MAI_FORMAT HW_REGISTER_RW( 0x7e902098 )
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#define HDMI_MAI_FORMAT_MASK 0xffffffff
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#define HDMI_MAI_FORMAT_WIDTH 32
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#define HDMI_MAI_FORMAT_RESET 0000000000
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#define HDMI_AUDIO_PACKET_CONFIG HW_REGISTER_RW( 0x7e90209c )
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#define HDMI_AUDIO_PACKET_CONFIG_MASK 0x3fffffff
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#define HDMI_AUDIO_PACKET_CONFIG_WIDTH 30
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#define HDMI_AUDIO_PACKET_CONFIG_RESET 0x21000403
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#define HDMI_RAM_PACKET_CONFIG HW_REGISTER_RW( 0x7e9020a0 )
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#define HDMI_RAM_PACKET_CONFIG_MASK 0x00013fff
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#define HDMI_RAM_PACKET_CONFIG_WIDTH 17
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#define HDMI_RAM_PACKET_CONFIG_RESET 0000000000
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#define HDMI_RAM_PACKET_STATUS HW_REGISTER_RW( 0x7e9020a4 )
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#define HDMI_RAM_PACKET_STATUS_MASK 0x00003fff
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#define HDMI_RAM_PACKET_STATUS_WIDTH 14
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#define HDMI_RAM_PACKET_STATUS_RESET 0000000000
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#define HDMI_CRP_CFG HW_REGISTER_RW( 0x7e9020a8 )
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#define HDMI_CRP_CFG_MASK 0x0fffffff
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#define HDMI_CRP_CFG_WIDTH 28
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#define HDMI_CRP_CFG_RESET 0x08000000
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#define HDMI_CTS_0 HW_REGISTER_RW( 0x7e9020ac )
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#define HDMI_CTS_0_MASK 0x000fffff
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#define HDMI_CTS_0_WIDTH 20
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#define HDMI_CTS_0_RESET 0000000000
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#define HDMI_CTS_1 HW_REGISTER_RW( 0x7e9020b0 )
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#define HDMI_CTS_1_MASK 0x000fffff
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#define HDMI_CTS_1_WIDTH 20
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#define HDMI_CTS_1_RESET 0000000000
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#define HDMI_CTS_PERIOD_0 HW_REGISTER_RW( 0x7e9020b4 )
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#define HDMI_CTS_PERIOD_0_MASK 0xff0fffff
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#define HDMI_CTS_PERIOD_0_WIDTH 32
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#define HDMI_CTS_PERIOD_0_RESET 0x010124f8
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#define HDMI_CTS_PERIOD_1 HW_REGISTER_RW( 0x7e9020b8 )
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#define HDMI_CTS_PERIOD_1_MASK 0xff0fffff
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#define HDMI_CTS_PERIOD_1_WIDTH 32
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#define HDMI_CTS_PERIOD_1_RESET 0x010124f8
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#define HDMI_BCH_CONFIGURATION HW_REGISTER_RW( 0x7e9020bc )
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#define HDMI_BCH_CONFIGURATION_MASK 0x000001ff
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#define HDMI_BCH_CONFIGURATION_WIDTH 9
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#define HDMI_BCH_CONFIGURATION_RESET 0x00000083
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#define HDMI_SCHEDULER_CONTROL HW_REGISTER_RW( 0x7e9020c0 )
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#define HDMI_SCHEDULER_CONTROL_MASK 0x003fff7f
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#define HDMI_SCHEDULER_CONTROL_WIDTH 22
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#define HDMI_SCHEDULER_CONTROL_RESET 0x000cb008
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#define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_BITS 21:18
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#define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_SET 0x003c0000
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#define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_CLR 0xffc3ffff
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#define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_MSB 21
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#define HDMI_SCHEDULER_CONTROL_VSYNC_RESET_VAL_LSB 18
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#define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_BITS 17:17
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#define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_SET 0x00020000
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#define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_CLR 0xfffdffff
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#define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_MSB 17
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#define HDMI_SCHEDULER_CONTROL_VSYNC_PHYST_EN_LSB 17
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#define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_BITS 16:16
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#define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_SET 0x00010000
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#define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_CLR 0xfffeffff
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#define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_MSB 16
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#define HDMI_SCHEDULER_CONTROL_HSYNC_PHYST_EN_LSB 16
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#define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_BITS 15:15
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#define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_SET 0x00008000
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#define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_CLR 0xffff7fff
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#define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_MSB 15
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#define HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT_LSB 15
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#define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_BITS 14:14
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#define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_SET 0x00004000
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#define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_CLR 0xffffbfff
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#define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_MSB 14
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#define HDMI_SCHEDULER_CONTROL_USE_POSTLN_AVOID_LSB 14
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#define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_BITS 13:8
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#define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_SET 0x00003f00
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#define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_CLR 0xffffc0ff
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#define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_MSB 13
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#define HDMI_SCHEDULER_CONTROL_POSTLN_AVOID_LSB 8
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#define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_BITS 6:6
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#define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_SET 0x00000040
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#define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_CLR 0xffffffbf
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#define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_MSB 6
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#define HDMI_SCHEDULER_CONTROL_ENC_ONLY_WHEN_AUTH_LSB 6
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#define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_BITS 5:5
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#define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_SET 0x00000020
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#define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_CLR 0xffffffdf
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#define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_MSB 5
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#define HDMI_SCHEDULER_CONTROL_IGN_VSYNC_PREDS_LSB 5
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#define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_BITS 4:4
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#define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_SET 0x00000010
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#define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_CLR 0xffffffef
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#define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_MSB 4
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#define HDMI_SCHEDULER_CONTROL_ALWS_REKEY_KEEPOUT_LSB 4
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#define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_BITS 3:3
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#define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_SET 0x00000008
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#define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_CLR 0xfffffff7
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#define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_MSB 3
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#define HDMI_SCHEDULER_CONTROL_ALWS_VERT_KEEPOUT_LSB 3
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#define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_BITS 2:2
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#define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_SET 0x00000004
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#define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_CLR 0xfffffffb
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#define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_MSB 2
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#define HDMI_SCHEDULER_CONTROL_USE_PREDICTS_LSB 2
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#define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_BITS 1:1
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#define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_SET 0x00000002
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#define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_CLR 0xfffffffd
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#define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_MSB 1
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#define HDMI_SCHEDULER_CONTROL_MODE_ACTIVE_LSB 1
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#define HDMI_SCHEDULER_CONTROL_MODE_REQ_BITS 0:0
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#define HDMI_SCHEDULER_CONTROL_MODE_REQ_SET 0x00000001
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#define HDMI_SCHEDULER_CONTROL_MODE_REQ_CLR 0xfffffffe
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#define HDMI_SCHEDULER_CONTROL_MODE_REQ_MSB 0
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#define HDMI_SCHEDULER_CONTROL_MODE_REQ_LSB 0
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#define HDMI_HORZA HW_REGISTER_RW( 0x7e9020c4 )
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#define HDMI_HORZA_MASK 0x00007fff
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#define HDMI_HORZA_WIDTH 15
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#define HDMI_HORZA_RESET 0x00000280
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#define HDMI_HORZA_MANUAL_VPOL_BITS 14:14
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#define HDMI_HORZA_MANUAL_VPOL_SET 0x00004000
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#define HDMI_HORZA_MANUAL_VPOL_CLR 0xffffbfff
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#define HDMI_HORZA_MANUAL_VPOL_MSB 14
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#define HDMI_HORZA_MANUAL_VPOL_LSB 14
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#define HDMI_HORZA_MANUAL_HPOL_BITS 13:13
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#define HDMI_HORZA_MANUAL_HPOL_SET 0x00002000
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#define HDMI_HORZA_MANUAL_HPOL_CLR 0xffffdfff
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#define HDMI_HORZA_MANUAL_HPOL_MSB 13
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#define HDMI_HORZA_MANUAL_HPOL_LSB 13
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#define HDMI_HORZA_MANUAL_HAP_BITS 12:0
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#define HDMI_HORZA_MANUAL_HAP_SET 0x00001fff
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#define HDMI_HORZA_MANUAL_HAP_CLR 0xffffe000
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#define HDMI_HORZA_MANUAL_HAP_MSB 12
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#define HDMI_HORZA_MANUAL_HAP_LSB 0
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#define HDMI_HORZB HW_REGISTER_RW( 0x7e9020c8 )
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#define HDMI_HORZB_MASK 0x3fffffff
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#define HDMI_HORZB_WIDTH 30
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#define HDMI_HORZB_RESET 0x03018010
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#define HDMI_HORZB_MANUAL_HBP_BITS 29:20
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#define HDMI_HORZB_MANUAL_HBP_SET 0x3ff00000
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#define HDMI_HORZB_MANUAL_HBP_CLR 0xc00fffff
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#define HDMI_HORZB_MANUAL_HBP_MSB 29
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#define HDMI_HORZB_MANUAL_HBP_LSB 20
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#define HDMI_HORZB_MANUAL_HSP_BITS 19:10
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#define HDMI_HORZB_MANUAL_HSP_SET 0x000ffc00
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#define HDMI_HORZB_MANUAL_HSP_CLR 0xfff003ff
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#define HDMI_HORZB_MANUAL_HSP_MSB 19
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#define HDMI_HORZB_MANUAL_HSP_LSB 10
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#define HDMI_HORZB_MANUAL_HFP_BITS 9:9
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#define HDMI_HORZB_MANUAL_HFP_SET 0x00000200
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#define HDMI_HORZB_MANUAL_HFP_CLR 0xfffffdff
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#define HDMI_HORZB_MANUAL_HFP_MSB 9
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#define HDMI_HORZB_MANUAL_HFP_LSB 9
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#define HDMI_VERTA0 HW_REGISTER_RW( 0x7e9020cc )
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#define HDMI_VERTA0_MASK 0x01ffffff
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#define HDMI_VERTA0_WIDTH 25
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#define HDMI_VERTA0_RESET 0x002141e0
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#define HDMI_VERTA0_MANUAL_VSP0_BITS 24:20
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#define HDMI_VERTA0_MANUAL_VSP0_SET 0x01f00000
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#define HDMI_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
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#define HDMI_VERTA0_MANUAL_VSP0_MSB 24
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#define HDMI_VERTA0_MANUAL_VSP0_LSB 20
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#define HDMI_VERTA0_MANUAL_VFP0_BITS 19:13
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#define HDMI_VERTA0_MANUAL_VFP0_SET 0x000fe000
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#define HDMI_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
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#define HDMI_VERTA0_MANUAL_VFP0_MSB 19
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#define HDMI_VERTA0_MANUAL_VFP0_LSB 13
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#define HDMI_VERTA0_MANUAL_VAL0_BITS 12:0
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#define HDMI_VERTA0_MANUAL_VAL0_SET 0x00001fff
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#define HDMI_VERTA0_MANUAL_VAL0_CLR 0xffffe000
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#define HDMI_VERTA0_MANUAL_VAL0_MSB 12
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#define HDMI_VERTA0_MANUAL_VAL0_LSB 0
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#define HDMI_VERTB0 HW_REGISTER_RW( 0x7e9020d0 )
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#define HDMI_VERTB0_MASK 0x003fffff
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#define HDMI_VERTB0_WIDTH 22
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#define HDMI_VERTB0_RESET 0x00000021
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#define HDMI_VERTB0_MANUAL_VSPO0_BITS 21:9
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#define HDMI_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
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#define HDMI_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
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#define HDMI_VERTB0_MANUAL_VSPO0_MSB 21
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#define HDMI_VERTB0_MANUAL_VSPO0_LSB 9
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#define HDMI_VERTB0_MANUAL_VBP0_BITS 8:8
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#define HDMI_VERTB0_MANUAL_VBP0_SET 0x00000100
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#define HDMI_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
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#define HDMI_VERTB0_MANUAL_VBP0_MSB 8
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#define HDMI_VERTB0_MANUAL_VBP0_LSB 8
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#define HDMI_VERTA1 HW_REGISTER_RW( 0x7e9020d4 )
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#define HDMI_VERTA1_MASK 0x01ffffff
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#define HDMI_VERTA1_WIDTH 25
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#define HDMI_VERTA1_RESET 0x002141e0
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#define HDMI_VERTA1_MANUAL_VSP1_BITS 24:20
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#define HDMI_VERTA1_MANUAL_VSP1_SET 0x01f00000
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#define HDMI_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
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#define HDMI_VERTA1_MANUAL_VSP1_MSB 24
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#define HDMI_VERTA1_MANUAL_VSP1_LSB 20
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#define HDMI_VERTA1_MANUAL_VFP1_BITS 19:13
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#define HDMI_VERTA1_MANUAL_VFP1_SET 0x000fe000
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#define HDMI_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
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#define HDMI_VERTA1_MANUAL_VFP1_MSB 19
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#define HDMI_VERTA1_MANUAL_VFP1_LSB 13
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#define HDMI_VERTA1_MANUAL_VAL1_BITS 12:0
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#define HDMI_VERTA1_MANUAL_VAL1_SET 0x00001fff
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#define HDMI_VERTA1_MANUAL_VAL1_CLR 0xffffe000
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#define HDMI_VERTA1_MANUAL_VAL1_MSB 12
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#define HDMI_VERTA1_MANUAL_VAL1_LSB 0
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#define HDMI_VERTB1 HW_REGISTER_RW( 0x7e9020d8 )
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#define HDMI_VERTB1_MASK 0x003fffff
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#define HDMI_VERTB1_WIDTH 22
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#define HDMI_VERTB1_RESET 0x00000021
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#define HDMI_VERTB1_MANUAL_VSPO1_BITS 21:9
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#define HDMI_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
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#define HDMI_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
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#define HDMI_VERTB1_MANUAL_VSPO1_MSB 21
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#define HDMI_VERTB1_MANUAL_VSPO1_LSB 9
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#define HDMI_VERTB1_MANUAL_VBP1_BITS 8:8
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#define HDMI_VERTB1_MANUAL_VBP1_SET 0x00000100
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#define HDMI_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
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#define HDMI_VERTB1_MANUAL_VBP1_MSB 8
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#define HDMI_VERTB1_MANUAL_VBP1_LSB 8
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#define HDMI_TEST HW_REGISTER_RW( 0x7e9020dc )
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#define HDMI_TEST_MASK 0x00000fff
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#define HDMI_TEST_WIDTH 12
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#define HDMI_TEST_RESET 0000000000
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#define HDMI_MBIST_TM HW_REGISTER_RW( 0x7e9020e0 )
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#define HDMI_MBIST_TM_MASK 0x00ffffff
|
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#define HDMI_MBIST_TM_WIDTH 24
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#define HDMI_MBIST_TM_RESET 0000000000
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#define HDMI_MISC_CONTROL HW_REGISTER_RW( 0x7e9020e4 )
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#define HDMI_MISC_CONTROL_MASK 0x7fffffff
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#define HDMI_MISC_CONTROL_WIDTH 31
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#define HDMI_MISC_CONTROL_RESET 0000000000
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#define HDMI_CEC_CNTRL_1 HW_REGISTER_RW( 0x7e9020e8 )
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#define HDMI_CEC_CNTRL_1_MASK 0xffffffff
|
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#define HDMI_CEC_CNTRL_1_WIDTH 32
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#define HDMI_CEC_CNTRL_1_RESET 0x0000e7be
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#define HDMI_CEC_CNTRL_2 HW_REGISTER_RW( 0x7e9020ec )
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#define HDMI_CEC_CNTRL_2_MASK 0x7fffffff
|
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#define HDMI_CEC_CNTRL_2_WIDTH 31
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#define HDMI_CEC_CNTRL_2_RESET 0x508d63d5
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#define HDMI_CEC_CNTRL_3 HW_REGISTER_RW( 0x7e9020f0 )
|
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#define HDMI_CEC_CNTRL_3_MASK 0xffffffff
|
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#define HDMI_CEC_CNTRL_3_WIDTH 32
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#define HDMI_CEC_CNTRL_3_RESET 0x96826f5c
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#define HDMI_CEC_CNTRL_4 HW_REGISTER_RW( 0x7e9020f4 )
|
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#define HDMI_CEC_CNTRL_4_MASK 0xffffffff
|
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#define HDMI_CEC_CNTRL_4_WIDTH 32
|
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#define HDMI_CEC_CNTRL_4_RESET 0xead4c3be
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#define HDMI_CEC_CNTRL_5 HW_REGISTER_RW( 0x7e9020f8 )
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#define HDMI_CEC_CNTRL_5_MASK 0x0fffffff
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#define HDMI_CEC_CNTRL_5_WIDTH 28
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#define HDMI_CEC_CNTRL_5_RESET 0x004cfff5
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#define HDMI_CEC_TX_DATA_1 HW_REGISTER_RW( 0x7e9020fc )
|
|
#define HDMI_CEC_TX_DATA_1_MASK 0xffffffff
|
|
#define HDMI_CEC_TX_DATA_1_WIDTH 32
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#define HDMI_CEC_TX_DATA_1_RESET 0000000000
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#define HDMI_CEC_TX_DATA_2 HW_REGISTER_RW( 0x7e902100 )
|
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#define HDMI_CEC_TX_DATA_2_MASK 0xffffffff
|
|
#define HDMI_CEC_TX_DATA_2_WIDTH 32
|
|
#define HDMI_CEC_TX_DATA_2_RESET 0000000000
|
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#define HDMI_CEC_TX_DATA_3 HW_REGISTER_RW( 0x7e902104 )
|
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#define HDMI_CEC_TX_DATA_3_MASK 0xffffffff
|
|
#define HDMI_CEC_TX_DATA_3_WIDTH 32
|
|
#define HDMI_CEC_TX_DATA_3_RESET 0000000000
|
|
#define HDMI_CEC_TX_DATA_4 HW_REGISTER_RW( 0x7e902108 )
|
|
#define HDMI_CEC_TX_DATA_4_MASK 0xffffffff
|
|
#define HDMI_CEC_TX_DATA_4_WIDTH 32
|
|
#define HDMI_CEC_TX_DATA_4_RESET 0000000000
|
|
#define HDMI_CEC_RX_DATA_1 HW_REGISTER_RW( 0x7e90210c )
|
|
#define HDMI_CEC_RX_DATA_1_MASK 0xffffffff
|
|
#define HDMI_CEC_RX_DATA_1_WIDTH 32
|
|
#define HDMI_CEC_RX_DATA_1_RESET 0000000000
|
|
#define HDMI_CEC_RX_DATA_2 HW_REGISTER_RW( 0x7e902110 )
|
|
#define HDMI_CEC_RX_DATA_2_MASK 0xffffffff
|
|
#define HDMI_CEC_RX_DATA_2_WIDTH 32
|
|
#define HDMI_CEC_RX_DATA_2_RESET 0000000000
|
|
#define HDMI_CEC_RX_DATA_3 HW_REGISTER_RW( 0x7e902114 )
|
|
#define HDMI_CEC_RX_DATA_3_MASK 0xffffffff
|
|
#define HDMI_CEC_RX_DATA_3_WIDTH 32
|
|
#define HDMI_CEC_RX_DATA_3_RESET 0000000000
|
|
#define HDMI_CEC_RX_DATA_4 HW_REGISTER_RW( 0x7e902118 )
|
|
#define HDMI_CEC_RX_DATA_4_MASK 0xffffffff
|
|
#define HDMI_CEC_RX_DATA_4_WIDTH 32
|
|
#define HDMI_CEC_RX_DATA_4_RESET 0000000000
|
|
#define HDMI_PACKET_FIFO_CTL HW_REGISTER_RW( 0x7e90211c )
|
|
#define HDMI_PACKET_FIFO_CTL_MASK 0x00000003
|
|
#define HDMI_PACKET_FIFO_CTL_WIDTH 2
|
|
#define HDMI_PACKET_FIFO_CTL_RESET 0000000000
|
|
#define HDMI_PACKET_FIFO_CFG HW_REGISTER_RW( 0x7e902120 )
|
|
#define HDMI_PACKET_FIFO_CFG_MASK 0x00000001
|
|
#define HDMI_PACKET_FIFO_CFG_WIDTH 1
|
|
#define HDMI_PACKET_FIFO_CFG_RESET 0000000000
|
|
#define HDMI_PACKET_FIFO_STATUS HW_REGISTER_RW( 0x7e902124 )
|
|
#define HDMI_PACKET_FIFO_STATUS_MASK 0x03073f1f
|
|
#define HDMI_PACKET_FIFO_STATUS_WIDTH 26
|
|
#define HDMI_PACKET_FIFO_STATUS_RESET 0x03010000
|
|
#define HDMI_DVO_TIMING_ADJUST_A HW_REGISTER_RW( 0x7e902128 )
|
|
#define HDMI_DVO_TIMING_ADJUST_A_MASK 0x000fffff
|
|
#define HDMI_DVO_TIMING_ADJUST_A_WIDTH 20
|
|
#define HDMI_DVO_TIMING_ADJUST_A_RESET 0x00088888
|
|
#define HDMI_DVO_TIMING_ADJUST_B HW_REGISTER_RW( 0x7e90212c )
|
|
#define HDMI_DVO_TIMING_ADJUST_B_MASK 0xffffffff
|
|
#define HDMI_DVO_TIMING_ADJUST_B_WIDTH 32
|
|
#define HDMI_DVO_TIMING_ADJUST_B_RESET 0x88888888
|
|
#define HDMI_DVO_TIMING_ADJUST_C HW_REGISTER_RW( 0x7e902130 )
|
|
#define HDMI_DVO_TIMING_ADJUST_C_MASK 0xffffffff
|
|
#define HDMI_DVO_TIMING_ADJUST_C_WIDTH 32
|
|
#define HDMI_DVO_TIMING_ADJUST_C_RESET 0x88888888
|
|
#define HDMI_DVO_TIMING_ADJUST_D HW_REGISTER_RW( 0x7e902134 )
|
|
#define HDMI_DVO_TIMING_ADJUST_D_MASK 0xffffffff
|
|
#define HDMI_DVO_TIMING_ADJUST_D_WIDTH 32
|
|
#define HDMI_DVO_TIMING_ADJUST_D_RESET 0x88888888
|
|
#define HDMI_DETECTED_HORZA HW_REGISTER_RW( 0x7e902138 )
|
|
#define HDMI_DETECTED_HORZA_MASK 0x00007fff
|
|
#define HDMI_DETECTED_HORZA_WIDTH 15
|
|
#define HDMI_DETECTED_HORZA_RESET 0x00000280
|
|
#define HDMI_DETECTED_HORZA_MANUAL_VPOL_BITS 14:14
|
|
#define HDMI_DETECTED_HORZA_MANUAL_VPOL_SET 0x00004000
|
|
#define HDMI_DETECTED_HORZA_MANUAL_VPOL_CLR 0xffffbfff
|
|
#define HDMI_DETECTED_HORZA_MANUAL_VPOL_MSB 14
|
|
#define HDMI_DETECTED_HORZA_MANUAL_VPOL_LSB 14
|
|
#define HDMI_DETECTED_HORZA_MANUAL_HPOL_BITS 13:13
|
|
#define HDMI_DETECTED_HORZA_MANUAL_HPOL_SET 0x00002000
|
|
#define HDMI_DETECTED_HORZA_MANUAL_HPOL_CLR 0xffffdfff
|
|
#define HDMI_DETECTED_HORZA_MANUAL_HPOL_MSB 13
|
|
#define HDMI_DETECTED_HORZA_MANUAL_HPOL_LSB 13
|
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#define HDMI_DETECTED_HORZA_MANUAL_HAP_BITS 12:0
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#define HDMI_DETECTED_HORZA_MANUAL_HAP_SET 0x00001fff
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#define HDMI_DETECTED_HORZA_MANUAL_HAP_CLR 0xffffe000
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#define HDMI_DETECTED_HORZA_MANUAL_HAP_MSB 12
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#define HDMI_DETECTED_HORZA_MANUAL_HAP_LSB 0
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#define HDMI_DETECTED_HORZB HW_REGISTER_RW( 0x7e90213c )
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#define HDMI_DETECTED_HORZB_MASK 0x3ffffe00
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#define HDMI_DETECTED_HORZB_WIDTH 30
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#define HDMI_DETECTED_HORZB_RESET 0x03018010
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#define HDMI_DETECTED_HORZB_MANUAL_HBP_BITS 29:20
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#define HDMI_DETECTED_HORZB_MANUAL_HBP_SET 0x3ff00000
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#define HDMI_DETECTED_HORZB_MANUAL_HBP_CLR 0xc00fffff
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#define HDMI_DETECTED_HORZB_MANUAL_HBP_MSB 29
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#define HDMI_DETECTED_HORZB_MANUAL_HBP_LSB 20
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#define HDMI_DETECTED_HORZB_MANUAL_HSP_BITS 19:10
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#define HDMI_DETECTED_HORZB_MANUAL_HSP_SET 0x000ffc00
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#define HDMI_DETECTED_HORZB_MANUAL_HSP_CLR 0xfff003ff
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#define HDMI_DETECTED_HORZB_MANUAL_HSP_MSB 19
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#define HDMI_DETECTED_HORZB_MANUAL_HSP_LSB 10
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#define HDMI_DETECTED_HORZB_MANUAL_HFP_BITS 9:9
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#define HDMI_DETECTED_HORZB_MANUAL_HFP_SET 0x00000200
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#define HDMI_DETECTED_HORZB_MANUAL_HFP_CLR 0xfffffdff
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#define HDMI_DETECTED_HORZB_MANUAL_HFP_MSB 9
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#define HDMI_DETECTED_HORZB_MANUAL_HFP_LSB 9
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#define HDMI_DETECTED_VERTA0 HW_REGISTER_RW( 0x7e902140 )
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#define HDMI_DETECTED_VERTA0_MASK 0x01ffffff
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#define HDMI_DETECTED_VERTA0_WIDTH 25
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#define HDMI_DETECTED_VERTA0_RESET 0x002141e0
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#define HDMI_DETECTED_VERTA0_MANUAL_VSP0_BITS 24:20
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#define HDMI_DETECTED_VERTA0_MANUAL_VSP0_SET 0x01f00000
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#define HDMI_DETECTED_VERTA0_MANUAL_VSP0_CLR 0xfe0fffff
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#define HDMI_DETECTED_VERTA0_MANUAL_VSP0_MSB 24
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#define HDMI_DETECTED_VERTA0_MANUAL_VSP0_LSB 20
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#define HDMI_DETECTED_VERTA0_MANUAL_VFP0_BITS 19:13
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#define HDMI_DETECTED_VERTA0_MANUAL_VFP0_SET 0x000fe000
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#define HDMI_DETECTED_VERTA0_MANUAL_VFP0_CLR 0xfff01fff
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#define HDMI_DETECTED_VERTA0_MANUAL_VFP0_MSB 19
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#define HDMI_DETECTED_VERTA0_MANUAL_VFP0_LSB 13
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#define HDMI_DETECTED_VERTA0_MANUAL_VAL0_BITS 12:0
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#define HDMI_DETECTED_VERTA0_MANUAL_VAL0_SET 0x00001fff
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#define HDMI_DETECTED_VERTA0_MANUAL_VAL0_CLR 0xffffe000
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#define HDMI_DETECTED_VERTA0_MANUAL_VAL0_MSB 12
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#define HDMI_DETECTED_VERTA0_MANUAL_VAL0_LSB 0
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#define HDMI_DETECTED_VERTB0 HW_REGISTER_RW( 0x7e902144 )
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#define HDMI_DETECTED_VERTB0_MASK 0x003fff00
|
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#define HDMI_DETECTED_VERTB0_WIDTH 22
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#define HDMI_DETECTED_VERTB0_RESET 0x00000021
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#define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_BITS 21:9
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#define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_SET 0x003ffe00
|
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#define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_CLR 0xffc001ff
|
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#define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_MSB 21
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#define HDMI_DETECTED_VERTB0_MANUAL_VSPO0_LSB 9
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#define HDMI_DETECTED_VERTB0_MANUAL_VBP0_BITS 8:8
|
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#define HDMI_DETECTED_VERTB0_MANUAL_VBP0_SET 0x00000100
|
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#define HDMI_DETECTED_VERTB0_MANUAL_VBP0_CLR 0xfffffeff
|
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#define HDMI_DETECTED_VERTB0_MANUAL_VBP0_MSB 8
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#define HDMI_DETECTED_VERTB0_MANUAL_VBP0_LSB 8
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#define HDMI_DETECTED_VERTA1 HW_REGISTER_RW( 0x7e902148 )
|
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#define HDMI_DETECTED_VERTA1_MASK 0x01ffffff
|
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#define HDMI_DETECTED_VERTA1_WIDTH 25
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#define HDMI_DETECTED_VERTA1_RESET 0x002141e0
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VSP1_BITS 24:20
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VSP1_SET 0x01f00000
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VSP1_CLR 0xfe0fffff
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VSP1_MSB 24
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#define HDMI_DETECTED_VERTA1_MANUAL_VSP1_LSB 20
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#define HDMI_DETECTED_VERTA1_MANUAL_VFP1_BITS 19:13
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#define HDMI_DETECTED_VERTA1_MANUAL_VFP1_SET 0x000fe000
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VFP1_CLR 0xfff01fff
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VFP1_MSB 19
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#define HDMI_DETECTED_VERTA1_MANUAL_VFP1_LSB 13
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#define HDMI_DETECTED_VERTA1_MANUAL_VAL1_BITS 12:0
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#define HDMI_DETECTED_VERTA1_MANUAL_VAL1_SET 0x00001fff
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VAL1_CLR 0xffffe000
|
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#define HDMI_DETECTED_VERTA1_MANUAL_VAL1_MSB 12
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#define HDMI_DETECTED_VERTA1_MANUAL_VAL1_LSB 0
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#define HDMI_DETECTED_VERTB1 HW_REGISTER_RW( 0x7e90214c )
|
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#define HDMI_DETECTED_VERTB1_MASK 0x003fff00
|
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#define HDMI_DETECTED_VERTB1_WIDTH 22
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#define HDMI_DETECTED_VERTB1_RESET 0x00000021
|
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#define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_BITS 21:9
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#define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_SET 0x003ffe00
|
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#define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_CLR 0xffc001ff
|
|
#define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_MSB 21
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#define HDMI_DETECTED_VERTB1_MANUAL_VSPO1_LSB 9
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#define HDMI_DETECTED_VERTB1_MANUAL_VBP1_BITS 8:8
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#define HDMI_DETECTED_VERTB1_MANUAL_VBP1_SET 0x00000100
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#define HDMI_DETECTED_VERTB1_MANUAL_VBP1_CLR 0xfffffeff
|
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#define HDMI_DETECTED_VERTB1_MANUAL_VBP1_MSB 8
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#define HDMI_DETECTED_VERTB1_MANUAL_VBP1_LSB 8
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#define HDMI_13_AUDIO_CFG_1 HW_REGISTER_RW( 0x7e902150 )
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#define HDMI_13_AUDIO_CFG_1_MASK 0x000003ff
|
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#define HDMI_13_AUDIO_CFG_1_WIDTH 10
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#define HDMI_13_AUDIO_CFG_1_RESET 0x000000c8
|
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#define HDMI_13_AUDIO_STATUS_1 HW_REGISTER_RW( 0x7e902154 )
|
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#define HDMI_13_AUDIO_STATUS_1_MASK 0x00000001
|
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#define HDMI_13_AUDIO_STATUS_1_WIDTH 1
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#define HDMI_13_AUDIO_STATUS_1_RESET 0000000000
|
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#define HDMI_HBR_AUDIO_PACKET_HEADER HW_REGISTER_RW( 0x7e902158 )
|
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#define HDMI_HBR_AUDIO_PACKET_HEADER_MASK 0x000fffff
|
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#define HDMI_HBR_AUDIO_PACKET_HEADER_WIDTH 20
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#define HDMI_HBR_AUDIO_PACKET_HEADER_RESET 0x00000009
|
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#define HDMI_POSTING_MASTER HW_REGISTER_RW( 0x7e90215c )
|
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#define HDMI_POSTING_MASTER_MASK 0x000000ff
|
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#define HDMI_POSTING_MASTER_WIDTH 8
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#define HDMI_POSTING_MASTER_RESET 0x000000ff
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#define HDMI_TX_PHY_TX_PHY_RESET_CTL HW_REGISTER_RW( 0x7e9022c0 )
|
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#define HDMI_TX_PHY_TX_PHY_RESET_CTL_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_RESET_CTL_WIDTH 32
|
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#define HDMI_TX_PHY_TX_PHY_RESET_CTL_RESET 0x003f01ff
|
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#define HDMI_TX_PHY_TX_PHY_CTL_0 HW_REGISTER_RW( 0x7e9022c4 )
|
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#define HDMI_TX_PHY_TX_PHY_CTL_0_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_CTL_0_WIDTH 32
|
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#define HDMI_TX_PHY_TX_PHY_CTL_0_RESET 0x8e000000
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#define HDMI_TX_PHY_TX_PHY_CTL_1 HW_REGISTER_RW( 0x7e9022c8 )
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#define HDMI_TX_PHY_TX_PHY_CTL_1_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_CTL_1_WIDTH 32
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#define HDMI_TX_PHY_TX_PHY_CTL_1_RESET 0x0404a808
|
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#define HDMI_TX_PHY_TX_PHY_CTL_2 HW_REGISTER_RW( 0x7e9022cc )
|
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#define HDMI_TX_PHY_TX_PHY_CTL_2_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_CTL_2_WIDTH 32
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#define HDMI_TX_PHY_TX_PHY_CTL_2_RESET 0x00a63004
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#define HDMI_TX_PHY_TX_PHY_PLL_CFG HW_REGISTER_RW( 0x7e9022d0 )
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#define HDMI_TX_PHY_TX_PHY_PLL_CFG_MASK 0xc3fbffff
|
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#define HDMI_TX_PHY_TX_PHY_PLL_CFG_WIDTH 32
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#define HDMI_TX_PHY_TX_PHY_PLL_CFG_RESET 0x07f80112
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#define HDMI_TX_PHY_TX_PHY_TMDS_CFG HW_REGISTER_RW( 0x7e9022d4 )
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#define HDMI_TX_PHY_TX_PHY_TMDS_CFG_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_TMDS_CFG_WIDTH 32
|
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#define HDMI_TX_PHY_TX_PHY_TMDS_CFG_RESET 0x0000001f
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#define HDMI_TX_PHY_TX_PHY_STATUS HW_REGISTER_RW( 0x7e9022d8 )
|
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#define HDMI_TX_PHY_TX_PHY_STATUS_MASK 0xffffffff
|
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#define HDMI_TX_PHY_TX_PHY_STATUS_WIDTH 32
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#define HDMI_TX_PHY_TX_PHY_STATUS_RESET 0000000000
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#define HDMI_TX_PHY_SPREAD_SPECTRUM HW_REGISTER_RW( 0x7e9022dc )
|
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#define HDMI_TX_PHY_SPREAD_SPECTRUM_MASK 0xffffffff
|
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#define HDMI_TX_PHY_SPREAD_SPECTRUM_WIDTH 32
|
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#define HDMI_TX_PHY_SPREAD_SPECTRUM_RESET 0x00003c00
|
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#define HDMI_TX_PHY_TX_PHY_SPARE HW_REGISTER_RW( 0x7e9022e0 )
|
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#define HDMI_TX_PHY_TX_PHY_SPARE_MASK 0xffffffff
|
|
#define HDMI_TX_PHY_TX_PHY_SPARE_WIDTH 32
|
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#define HDMI_TX_PHY_TX_PHY_SPARE_RESET 0xffff0000
|
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#define HDMI_CPU_STATUS HW_REGISTER_RW( 0x7e902340 )
|
|
#define HDMI_CPU_STATUS_MASK 0xffffffff
|
|
#define HDMI_CPU_STATUS_WIDTH 32
|
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#define HDMI_CPU_STATUS_RESET 0000000000
|
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#define HDMI_CPU_SET HW_REGISTER_RW( 0x7e902344 )
|
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#define HDMI_CPU_SET_MASK 0xffffffff
|
|
#define HDMI_CPU_SET_WIDTH 32
|
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#define HDMI_CPU_SET_RESET 0000000000
|
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#define HDMI_CPU_CLEAR HW_REGISTER_RW( 0x7e902348 )
|
|
#define HDMI_CPU_CLEAR_MASK 0xffffffff
|
|
#define HDMI_CPU_CLEAR_WIDTH 32
|
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#define HDMI_CPU_CLEAR_RESET 0000000000
|
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#define HDMI_CPU_MASK_STATUS HW_REGISTER_RW( 0x7e90234c )
|
|
#define HDMI_CPU_MASK_STATUS_MASK 0xffffffff
|
|
#define HDMI_CPU_MASK_STATUS_WIDTH 32
|
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#define HDMI_CPU_MASK_STATUS_RESET 0x0001ffff
|
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#define HDMI_CPU_MASK_SET HW_REGISTER_RW( 0x7e902350 )
|
|
#define HDMI_CPU_MASK_SET_MASK 0xffffffff
|
|
#define HDMI_CPU_MASK_SET_WIDTH 32
|
|
#define HDMI_CPU_MASK_SET_RESET 0x0001ffff
|
|
#define HDMI_CPU_MASK_CLEAR HW_REGISTER_RW( 0x7e902354 )
|
|
#define HDMI_CPU_MASK_CLEAR_MASK 0xffffffff
|
|
#define HDMI_CPU_MASK_CLEAR_WIDTH 32
|
|
#define HDMI_CPU_MASK_CLEAR_RESET 0x0001ffff
|
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#define HDMI_RAM_GCP_0 HW_REGISTER_RW( 0x7e902400 )
|
|
#define HDMI_RAM_GCP_0_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_0_WIDTH 32
|
|
#define HDMI_RAM_GCP_0_RESET 0000000000
|
|
#define HDMI_RAM_GCP_1 HW_REGISTER_RW( 0x7e902404 )
|
|
#define HDMI_RAM_GCP_1_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_1_WIDTH 32
|
|
#define HDMI_RAM_GCP_1_RESET 0000000000
|
|
#define HDMI_RAM_GCP_2 HW_REGISTER_RW( 0x7e902408 )
|
|
#define HDMI_RAM_GCP_2_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_2_WIDTH 32
|
|
#define HDMI_RAM_GCP_2_RESET 0000000000
|
|
#define HDMI_RAM_GCP_3 HW_REGISTER_RW( 0x7e90240c )
|
|
#define HDMI_RAM_GCP_3_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_3_WIDTH 32
|
|
#define HDMI_RAM_GCP_3_RESET 0000000000
|
|
#define HDMI_RAM_GCP_4 HW_REGISTER_RW( 0x7e902410 )
|
|
#define HDMI_RAM_GCP_4_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_4_WIDTH 32
|
|
#define HDMI_RAM_GCP_4_RESET 0000000000
|
|
#define HDMI_RAM_GCP_5 HW_REGISTER_RW( 0x7e902414 )
|
|
#define HDMI_RAM_GCP_5_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_5_WIDTH 32
|
|
#define HDMI_RAM_GCP_5_RESET 0000000000
|
|
#define HDMI_RAM_GCP_6 HW_REGISTER_RW( 0x7e902418 )
|
|
#define HDMI_RAM_GCP_6_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_6_WIDTH 32
|
|
#define HDMI_RAM_GCP_6_RESET 0000000000
|
|
#define HDMI_RAM_GCP_7 HW_REGISTER_RW( 0x7e90241c )
|
|
#define HDMI_RAM_GCP_7_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_7_WIDTH 32
|
|
#define HDMI_RAM_GCP_7_RESET 0000000000
|
|
#define HDMI_RAM_GCP_8 HW_REGISTER_RW( 0x7e902420 )
|
|
#define HDMI_RAM_GCP_8_MASK 0xffffffff
|
|
#define HDMI_RAM_GCP_8_WIDTH 32
|
|
#define HDMI_RAM_GCP_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_0 HW_REGISTER_RW( 0x7e902424 )
|
|
#define HDMI_RAM_PACKET_1_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_1 HW_REGISTER_RW( 0x7e902428 )
|
|
#define HDMI_RAM_PACKET_1_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_2 HW_REGISTER_RW( 0x7e90242c )
|
|
#define HDMI_RAM_PACKET_1_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_3 HW_REGISTER_RW( 0x7e902430 )
|
|
#define HDMI_RAM_PACKET_1_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_4 HW_REGISTER_RW( 0x7e902434 )
|
|
#define HDMI_RAM_PACKET_1_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_5 HW_REGISTER_RW( 0x7e902438 )
|
|
#define HDMI_RAM_PACKET_1_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_6 HW_REGISTER_RW( 0x7e90243c )
|
|
#define HDMI_RAM_PACKET_1_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_7 HW_REGISTER_RW( 0x7e902440 )
|
|
#define HDMI_RAM_PACKET_1_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_1_8 HW_REGISTER_RW( 0x7e902444 )
|
|
#define HDMI_RAM_PACKET_1_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_1_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_1_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_0 HW_REGISTER_RW( 0x7e902448 )
|
|
#define HDMI_RAM_PACKET_2_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_1 HW_REGISTER_RW( 0x7e90244c )
|
|
#define HDMI_RAM_PACKET_2_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_2 HW_REGISTER_RW( 0x7e902450 )
|
|
#define HDMI_RAM_PACKET_2_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_3 HW_REGISTER_RW( 0x7e902454 )
|
|
#define HDMI_RAM_PACKET_2_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_4 HW_REGISTER_RW( 0x7e902458 )
|
|
#define HDMI_RAM_PACKET_2_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_5 HW_REGISTER_RW( 0x7e90245c )
|
|
#define HDMI_RAM_PACKET_2_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_6 HW_REGISTER_RW( 0x7e902460 )
|
|
#define HDMI_RAM_PACKET_2_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_7 HW_REGISTER_RW( 0x7e902464 )
|
|
#define HDMI_RAM_PACKET_2_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_2_8 HW_REGISTER_RW( 0x7e902468 )
|
|
#define HDMI_RAM_PACKET_2_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_2_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_2_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_0 HW_REGISTER_RW( 0x7e90246c )
|
|
#define HDMI_RAM_PACKET_3_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_1 HW_REGISTER_RW( 0x7e902470 )
|
|
#define HDMI_RAM_PACKET_3_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_2 HW_REGISTER_RW( 0x7e902474 )
|
|
#define HDMI_RAM_PACKET_3_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_3 HW_REGISTER_RW( 0x7e902478 )
|
|
#define HDMI_RAM_PACKET_3_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_4 HW_REGISTER_RW( 0x7e90247c )
|
|
#define HDMI_RAM_PACKET_3_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_5 HW_REGISTER_RW( 0x7e902480 )
|
|
#define HDMI_RAM_PACKET_3_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_6 HW_REGISTER_RW( 0x7e902484 )
|
|
#define HDMI_RAM_PACKET_3_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_7 HW_REGISTER_RW( 0x7e902488 )
|
|
#define HDMI_RAM_PACKET_3_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_3_8 HW_REGISTER_RW( 0x7e90248c )
|
|
#define HDMI_RAM_PACKET_3_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_3_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_3_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_0 HW_REGISTER_RW( 0x7e902490 )
|
|
#define HDMI_RAM_PACKET_4_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_1 HW_REGISTER_RW( 0x7e902494 )
|
|
#define HDMI_RAM_PACKET_4_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_2 HW_REGISTER_RW( 0x7e902498 )
|
|
#define HDMI_RAM_PACKET_4_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_3 HW_REGISTER_RW( 0x7e90249c )
|
|
#define HDMI_RAM_PACKET_4_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_4 HW_REGISTER_RW( 0x7e9024a0 )
|
|
#define HDMI_RAM_PACKET_4_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_5 HW_REGISTER_RW( 0x7e9024a4 )
|
|
#define HDMI_RAM_PACKET_4_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_6 HW_REGISTER_RW( 0x7e9024a8 )
|
|
#define HDMI_RAM_PACKET_4_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_7 HW_REGISTER_RW( 0x7e9024ac )
|
|
#define HDMI_RAM_PACKET_4_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_4_8 HW_REGISTER_RW( 0x7e9024b0 )
|
|
#define HDMI_RAM_PACKET_4_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_4_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_4_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_0 HW_REGISTER_RW( 0x7e9024b4 )
|
|
#define HDMI_RAM_PACKET_5_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_1 HW_REGISTER_RW( 0x7e9024b8 )
|
|
#define HDMI_RAM_PACKET_5_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_2 HW_REGISTER_RW( 0x7e9024bc )
|
|
#define HDMI_RAM_PACKET_5_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_3 HW_REGISTER_RW( 0x7e9024c0 )
|
|
#define HDMI_RAM_PACKET_5_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_4 HW_REGISTER_RW( 0x7e9024c4 )
|
|
#define HDMI_RAM_PACKET_5_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_5 HW_REGISTER_RW( 0x7e9024c8 )
|
|
#define HDMI_RAM_PACKET_5_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_6 HW_REGISTER_RW( 0x7e9024cc )
|
|
#define HDMI_RAM_PACKET_5_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_7 HW_REGISTER_RW( 0x7e9024d0 )
|
|
#define HDMI_RAM_PACKET_5_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_5_8 HW_REGISTER_RW( 0x7e9024d4 )
|
|
#define HDMI_RAM_PACKET_5_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_5_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_5_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_0 HW_REGISTER_RW( 0x7e9024d8 )
|
|
#define HDMI_RAM_PACKET_6_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_1 HW_REGISTER_RW( 0x7e9024dc )
|
|
#define HDMI_RAM_PACKET_6_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_2 HW_REGISTER_RW( 0x7e9024e0 )
|
|
#define HDMI_RAM_PACKET_6_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_3 HW_REGISTER_RW( 0x7e9024e4 )
|
|
#define HDMI_RAM_PACKET_6_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_4 HW_REGISTER_RW( 0x7e9024e8 )
|
|
#define HDMI_RAM_PACKET_6_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_5 HW_REGISTER_RW( 0x7e9024ec )
|
|
#define HDMI_RAM_PACKET_6_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_6 HW_REGISTER_RW( 0x7e9024f0 )
|
|
#define HDMI_RAM_PACKET_6_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_7 HW_REGISTER_RW( 0x7e9024f4 )
|
|
#define HDMI_RAM_PACKET_6_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_6_8 HW_REGISTER_RW( 0x7e9024f8 )
|
|
#define HDMI_RAM_PACKET_6_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_6_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_6_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_0 HW_REGISTER_RW( 0x7e9024fc )
|
|
#define HDMI_RAM_PACKET_7_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_1 HW_REGISTER_RW( 0x7e902500 )
|
|
#define HDMI_RAM_PACKET_7_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_2 HW_REGISTER_RW( 0x7e902504 )
|
|
#define HDMI_RAM_PACKET_7_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_3 HW_REGISTER_RW( 0x7e902508 )
|
|
#define HDMI_RAM_PACKET_7_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_4 HW_REGISTER_RW( 0x7e90250c )
|
|
#define HDMI_RAM_PACKET_7_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_5 HW_REGISTER_RW( 0x7e902510 )
|
|
#define HDMI_RAM_PACKET_7_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_6 HW_REGISTER_RW( 0x7e902514 )
|
|
#define HDMI_RAM_PACKET_7_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_7 HW_REGISTER_RW( 0x7e902518 )
|
|
#define HDMI_RAM_PACKET_7_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_7_8 HW_REGISTER_RW( 0x7e90251c )
|
|
#define HDMI_RAM_PACKET_7_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_7_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_7_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_0 HW_REGISTER_RW( 0x7e902520 )
|
|
#define HDMI_RAM_PACKET_8_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_1 HW_REGISTER_RW( 0x7e902524 )
|
|
#define HDMI_RAM_PACKET_8_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_2 HW_REGISTER_RW( 0x7e902528 )
|
|
#define HDMI_RAM_PACKET_8_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_3 HW_REGISTER_RW( 0x7e90252c )
|
|
#define HDMI_RAM_PACKET_8_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_4 HW_REGISTER_RW( 0x7e902530 )
|
|
#define HDMI_RAM_PACKET_8_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_5 HW_REGISTER_RW( 0x7e902534 )
|
|
#define HDMI_RAM_PACKET_8_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_6 HW_REGISTER_RW( 0x7e902538 )
|
|
#define HDMI_RAM_PACKET_8_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_7 HW_REGISTER_RW( 0x7e90253c )
|
|
#define HDMI_RAM_PACKET_8_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_8_8 HW_REGISTER_RW( 0x7e902540 )
|
|
#define HDMI_RAM_PACKET_8_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_8_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_8_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_0 HW_REGISTER_RW( 0x7e902544 )
|
|
#define HDMI_RAM_PACKET_9_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_1 HW_REGISTER_RW( 0x7e902548 )
|
|
#define HDMI_RAM_PACKET_9_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_2 HW_REGISTER_RW( 0x7e90254c )
|
|
#define HDMI_RAM_PACKET_9_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_3 HW_REGISTER_RW( 0x7e902550 )
|
|
#define HDMI_RAM_PACKET_9_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_4 HW_REGISTER_RW( 0x7e902554 )
|
|
#define HDMI_RAM_PACKET_9_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_5 HW_REGISTER_RW( 0x7e902558 )
|
|
#define HDMI_RAM_PACKET_9_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_6 HW_REGISTER_RW( 0x7e90255c )
|
|
#define HDMI_RAM_PACKET_9_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_7 HW_REGISTER_RW( 0x7e902560 )
|
|
#define HDMI_RAM_PACKET_9_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_9_8 HW_REGISTER_RW( 0x7e902564 )
|
|
#define HDMI_RAM_PACKET_9_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_9_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_9_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_0 HW_REGISTER_RW( 0x7e902568 )
|
|
#define HDMI_RAM_PACKET_10_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_1 HW_REGISTER_RW( 0x7e90256c )
|
|
#define HDMI_RAM_PACKET_10_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_2 HW_REGISTER_RW( 0x7e902570 )
|
|
#define HDMI_RAM_PACKET_10_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_3 HW_REGISTER_RW( 0x7e902574 )
|
|
#define HDMI_RAM_PACKET_10_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_4 HW_REGISTER_RW( 0x7e902578 )
|
|
#define HDMI_RAM_PACKET_10_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_4_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_5 HW_REGISTER_RW( 0x7e90257c )
|
|
#define HDMI_RAM_PACKET_10_5_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_5_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_5_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_6 HW_REGISTER_RW( 0x7e902580 )
|
|
#define HDMI_RAM_PACKET_10_6_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_6_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_6_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_7 HW_REGISTER_RW( 0x7e902584 )
|
|
#define HDMI_RAM_PACKET_10_7_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_7_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_7_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_10_8 HW_REGISTER_RW( 0x7e902588 )
|
|
#define HDMI_RAM_PACKET_10_8_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_10_8_WIDTH 32
|
|
#define HDMI_RAM_PACKET_10_8_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_11_0 HW_REGISTER_RW( 0x7e90258c )
|
|
#define HDMI_RAM_PACKET_11_0_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_11_0_WIDTH 32
|
|
#define HDMI_RAM_PACKET_11_0_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_11_1 HW_REGISTER_RW( 0x7e902590 )
|
|
#define HDMI_RAM_PACKET_11_1_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_11_1_WIDTH 32
|
|
#define HDMI_RAM_PACKET_11_1_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_11_2 HW_REGISTER_RW( 0x7e902594 )
|
|
#define HDMI_RAM_PACKET_11_2_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_11_2_WIDTH 32
|
|
#define HDMI_RAM_PACKET_11_2_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_11_3 HW_REGISTER_RW( 0x7e902598 )
|
|
#define HDMI_RAM_PACKET_11_3_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_11_3_WIDTH 32
|
|
#define HDMI_RAM_PACKET_11_3_RESET 0000000000
|
|
#define HDMI_RAM_PACKET_11_4 HW_REGISTER_RW( 0x7e90259c )
|
|
#define HDMI_RAM_PACKET_11_4_MASK 0xffffffff
|
|
#define HDMI_RAM_PACKET_11_4_WIDTH 32
|
|
#define HDMI_RAM_PACKET_11_4_RESET 0000000000
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#define HDMI_RAM_PACKET_11_5 HW_REGISTER_RW( 0x7e9025a0 )
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#define HDMI_RAM_PACKET_11_5_MASK 0xffffffff
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#define HDMI_RAM_PACKET_11_5_WIDTH 32
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#define HDMI_RAM_PACKET_11_5_RESET 0000000000
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#define HDMI_RAM_PACKET_11_6 HW_REGISTER_RW( 0x7e9025a4 )
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#define HDMI_RAM_PACKET_11_6_MASK 0xffffffff
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#define HDMI_RAM_PACKET_11_6_WIDTH 32
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#define HDMI_RAM_PACKET_11_6_RESET 0000000000
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#define HDMI_RAM_PACKET_11_7 HW_REGISTER_RW( 0x7e9025a8 )
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#define HDMI_RAM_PACKET_11_7_MASK 0xffffffff
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#define HDMI_RAM_PACKET_11_7_WIDTH 32
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#define HDMI_RAM_PACKET_11_7_RESET 0000000000
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#define HDMI_RAM_PACKET_11_8 HW_REGISTER_RW( 0x7e9025ac )
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#define HDMI_RAM_PACKET_11_8_MASK 0xffffffff
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#define HDMI_RAM_PACKET_11_8_WIDTH 32
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#define HDMI_RAM_PACKET_11_8_RESET 0000000000
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#define HDMI_RAM_PACKET_12_0 HW_REGISTER_RW( 0x7e9025b0 )
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#define HDMI_RAM_PACKET_12_0_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_0_WIDTH 32
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#define HDMI_RAM_PACKET_12_0_RESET 0000000000
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#define HDMI_RAM_PACKET_12_1 HW_REGISTER_RW( 0x7e9025b4 )
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#define HDMI_RAM_PACKET_12_1_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_1_WIDTH 32
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#define HDMI_RAM_PACKET_12_1_RESET 0000000000
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#define HDMI_RAM_PACKET_12_2 HW_REGISTER_RW( 0x7e9025b8 )
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#define HDMI_RAM_PACKET_12_2_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_2_WIDTH 32
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#define HDMI_RAM_PACKET_12_2_RESET 0000000000
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#define HDMI_RAM_PACKET_12_3 HW_REGISTER_RW( 0x7e9025bc )
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#define HDMI_RAM_PACKET_12_3_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_3_WIDTH 32
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#define HDMI_RAM_PACKET_12_3_RESET 0000000000
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#define HDMI_RAM_PACKET_12_4 HW_REGISTER_RW( 0x7e9025c0 )
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#define HDMI_RAM_PACKET_12_4_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_4_WIDTH 32
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#define HDMI_RAM_PACKET_12_4_RESET 0000000000
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#define HDMI_RAM_PACKET_12_5 HW_REGISTER_RW( 0x7e9025c4 )
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#define HDMI_RAM_PACKET_12_5_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_5_WIDTH 32
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#define HDMI_RAM_PACKET_12_5_RESET 0000000000
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#define HDMI_RAM_PACKET_12_6 HW_REGISTER_RW( 0x7e9025c8 )
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#define HDMI_RAM_PACKET_12_6_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_6_WIDTH 32
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#define HDMI_RAM_PACKET_12_6_RESET 0000000000
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#define HDMI_RAM_PACKET_12_7 HW_REGISTER_RW( 0x7e9025cc )
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#define HDMI_RAM_PACKET_12_7_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_7_WIDTH 32
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#define HDMI_RAM_PACKET_12_7_RESET 0000000000
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#define HDMI_RAM_PACKET_12_8 HW_REGISTER_RW( 0x7e9025d0 )
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#define HDMI_RAM_PACKET_12_8_MASK 0xffffffff
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#define HDMI_RAM_PACKET_12_8_WIDTH 32
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#define HDMI_RAM_PACKET_12_8_RESET 0000000000
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#define HDMI_RAM_PACKET_13_0 HW_REGISTER_RW( 0x7e9025d4 )
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#define HDMI_RAM_PACKET_13_0_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_0_WIDTH 32
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#define HDMI_RAM_PACKET_13_0_RESET 0000000000
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#define HDMI_RAM_PACKET_13_1 HW_REGISTER_RW( 0x7e9025d8 )
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#define HDMI_RAM_PACKET_13_1_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_1_WIDTH 32
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#define HDMI_RAM_PACKET_13_1_RESET 0000000000
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#define HDMI_RAM_PACKET_13_2 HW_REGISTER_RW( 0x7e9025dc )
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#define HDMI_RAM_PACKET_13_2_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_2_WIDTH 32
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#define HDMI_RAM_PACKET_13_2_RESET 0000000000
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#define HDMI_RAM_PACKET_13_3 HW_REGISTER_RW( 0x7e9025e0 )
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#define HDMI_RAM_PACKET_13_3_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_3_WIDTH 32
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#define HDMI_RAM_PACKET_13_3_RESET 0000000000
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#define HDMI_RAM_PACKET_13_4 HW_REGISTER_RW( 0x7e9025e4 )
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#define HDMI_RAM_PACKET_13_4_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_4_WIDTH 32
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#define HDMI_RAM_PACKET_13_4_RESET 0000000000
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#define HDMI_RAM_PACKET_13_5 HW_REGISTER_RW( 0x7e9025e8 )
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#define HDMI_RAM_PACKET_13_5_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_5_WIDTH 32
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#define HDMI_RAM_PACKET_13_5_RESET 0000000000
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#define HDMI_RAM_PACKET_13_6 HW_REGISTER_RW( 0x7e9025ec )
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#define HDMI_RAM_PACKET_13_6_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_6_WIDTH 32
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#define HDMI_RAM_PACKET_13_6_RESET 0000000000
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#define HDMI_RAM_PACKET_13_7 HW_REGISTER_RW( 0x7e9025f0 )
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#define HDMI_RAM_PACKET_13_7_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_7_WIDTH 32
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#define HDMI_RAM_PACKET_13_7_RESET 0000000000
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#define HDMI_RAM_PACKET_13_8 HW_REGISTER_RW( 0x7e9025f4 )
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#define HDMI_RAM_PACKET_13_8_MASK 0xffffffff
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#define HDMI_RAM_PACKET_13_8_WIDTH 32
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#define HDMI_RAM_PACKET_13_8_RESET 0000000000
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