428 lines
30 KiB
C
Executable File
428 lines
30 KiB
C
Executable File
// This file was generated by the create_regs script
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#define I2C_SPI_SLV_BASE 0x7e214000
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#define I2C_SPI_SLV_APB_ID 0x73506783
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#define I2C_SPI_SLV_DR HW_REGISTER_RW( 0x7e214000 )
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#define I2C_SPI_SLV_DR_MASK 0xffff3fff
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#define I2C_SPI_SLV_DR_WIDTH 32
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#define I2C_SPI_SLV_DR_RESET 0x00120000
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#define I2C_SPI_SLV_DR_DATA_BITS 7:0
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#define I2C_SPI_SLV_DR_DATA_SET 0x000000ff
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#define I2C_SPI_SLV_DR_DATA_CLR 0xffffff00
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#define I2C_SPI_SLV_DR_DATA_MSB 7
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#define I2C_SPI_SLV_DR_DATA_LSB 0
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#define I2C_SPI_SLV_DR_OE_BITS 8:8
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#define I2C_SPI_SLV_DR_OE_SET 0x00000100
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#define I2C_SPI_SLV_DR_OE_CLR 0xfffffeff
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#define I2C_SPI_SLV_DR_OE_MSB 8
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#define I2C_SPI_SLV_DR_OE_LSB 8
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#define I2C_SPI_SLV_DR_UE_BITS 9:9
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#define I2C_SPI_SLV_DR_UE_SET 0x00000200
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#define I2C_SPI_SLV_DR_UE_CLR 0xfffffdff
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#define I2C_SPI_SLV_DR_UE_MSB 9
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#define I2C_SPI_SLV_DR_UE_LSB 9
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#define I2C_SPI_SLV_DR_TXDMAPREQ_BITS 10:10
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#define I2C_SPI_SLV_DR_TXDMAPREQ_SET 0x00000400
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#define I2C_SPI_SLV_DR_TXDMAPREQ_CLR 0xfffffbff
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#define I2C_SPI_SLV_DR_TXDMAPREQ_MSB 10
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#define I2C_SPI_SLV_DR_TXDMAPREQ_LSB 10
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#define I2C_SPI_SLV_DR_TXDMABREQ_BITS 11:11
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#define I2C_SPI_SLV_DR_TXDMABREQ_SET 0x00000800
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#define I2C_SPI_SLV_DR_TXDMABREQ_CLR 0xfffff7ff
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#define I2C_SPI_SLV_DR_TXDMABREQ_MSB 11
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#define I2C_SPI_SLV_DR_TXDMABREQ_LSB 11
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#define I2C_SPI_SLV_DR_RXDMAPREQ_BITS 12:12
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#define I2C_SPI_SLV_DR_RXDMAPREQ_SET 0x00001000
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#define I2C_SPI_SLV_DR_RXDMAPREQ_CLR 0xffffefff
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#define I2C_SPI_SLV_DR_RXDMAPREQ_MSB 12
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#define I2C_SPI_SLV_DR_RXDMAPREQ_LSB 12
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#define I2C_SPI_SLV_DR_RXDMABREQ_BITS 13:13
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#define I2C_SPI_SLV_DR_RXDMABREQ_SET 0x00002000
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#define I2C_SPI_SLV_DR_RXDMABREQ_CLR 0xffffdfff
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#define I2C_SPI_SLV_DR_RXDMABREQ_MSB 13
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#define I2C_SPI_SLV_DR_RXDMABREQ_LSB 13
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#define I2C_SPI_SLV_DR_TXBUSY_BITS 16:16
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#define I2C_SPI_SLV_DR_TXBUSY_SET 0x00010000
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#define I2C_SPI_SLV_DR_TXBUSY_CLR 0xfffeffff
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#define I2C_SPI_SLV_DR_TXBUSY_MSB 16
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#define I2C_SPI_SLV_DR_TXBUSY_LSB 16
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#define I2C_SPI_SLV_DR_RXFE_BITS 17:17
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#define I2C_SPI_SLV_DR_RXFE_SET 0x00020000
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#define I2C_SPI_SLV_DR_RXFE_CLR 0xfffdffff
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#define I2C_SPI_SLV_DR_RXFE_MSB 17
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#define I2C_SPI_SLV_DR_RXFE_LSB 17
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#define I2C_SPI_SLV_DR_TXFF_BITS 18:18
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#define I2C_SPI_SLV_DR_TXFF_SET 0x00040000
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#define I2C_SPI_SLV_DR_TXFF_CLR 0xfffbffff
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#define I2C_SPI_SLV_DR_TXFF_MSB 18
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#define I2C_SPI_SLV_DR_TXFF_LSB 18
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#define I2C_SPI_SLV_DR_RXFF_BITS 19:19
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#define I2C_SPI_SLV_DR_RXFF_SET 0x00080000
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#define I2C_SPI_SLV_DR_RXFF_CLR 0xfff7ffff
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#define I2C_SPI_SLV_DR_RXFF_MSB 19
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#define I2C_SPI_SLV_DR_RXFF_LSB 19
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#define I2C_SPI_SLV_DR_TXFE_BITS 20:20
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#define I2C_SPI_SLV_DR_TXFE_SET 0x00100000
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#define I2C_SPI_SLV_DR_TXFE_CLR 0xffefffff
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#define I2C_SPI_SLV_DR_TXFE_MSB 20
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#define I2C_SPI_SLV_DR_TXFE_LSB 20
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#define I2C_SPI_SLV_DR_RXBUSY_BITS 21:21
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#define I2C_SPI_SLV_DR_RXBUSY_SET 0x00200000
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#define I2C_SPI_SLV_DR_RXBUSY_CLR 0xffdfffff
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#define I2C_SPI_SLV_DR_RXBUSY_MSB 21
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#define I2C_SPI_SLV_DR_RXBUSY_LSB 21
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#define I2C_SPI_SLV_DR_TXFLEVEL_BITS 26:22
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#define I2C_SPI_SLV_DR_TXFLEVEL_SET 0x07c00000
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#define I2C_SPI_SLV_DR_TXFLEVEL_CLR 0xf83fffff
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#define I2C_SPI_SLV_DR_TXFLEVEL_MSB 26
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#define I2C_SPI_SLV_DR_TXFLEVEL_LSB 22
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#define I2C_SPI_SLV_DR_RXFLEVEL_BITS 31:27
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#define I2C_SPI_SLV_DR_RXFLEVEL_SET 0xf8000000
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#define I2C_SPI_SLV_DR_RXFLEVEL_CLR 0x07ffffff
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#define I2C_SPI_SLV_DR_RXFLEVEL_MSB 31
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#define I2C_SPI_SLV_DR_RXFLEVEL_LSB 27
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#define I2C_SPI_SLV_RSR HW_REGISTER_RW( 0x7e214004 )
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#define I2C_SPI_SLV_RSR_MASK 0x0000003f
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#define I2C_SPI_SLV_RSR_WIDTH 6
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#define I2C_SPI_SLV_RSR_RESET 0000000000
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#define I2C_SPI_SLV_RSR_OE_BITS 0:0
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#define I2C_SPI_SLV_RSR_OE_SET 0x00000001
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#define I2C_SPI_SLV_RSR_OE_CLR 0xfffffffe
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#define I2C_SPI_SLV_RSR_OE_MSB 0
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#define I2C_SPI_SLV_RSR_OE_LSB 0
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#define I2C_SPI_SLV_RSR_UE_BITS 1:1
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#define I2C_SPI_SLV_RSR_UE_SET 0x00000002
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#define I2C_SPI_SLV_RSR_UE_CLR 0xfffffffd
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#define I2C_SPI_SLV_RSR_UE_MSB 1
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#define I2C_SPI_SLV_RSR_UE_LSB 1
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#define I2C_SPI_SLV_RSR_TXDMAPREQ_BITS 2:2
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#define I2C_SPI_SLV_RSR_TXDMAPREQ_SET 0x00000004
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#define I2C_SPI_SLV_RSR_TXDMAPREQ_CLR 0xfffffffb
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#define I2C_SPI_SLV_RSR_TXDMAPREQ_MSB 2
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#define I2C_SPI_SLV_RSR_TXDMAPREQ_LSB 2
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#define I2C_SPI_SLV_RSR_TXDMABREQ_BITS 3:3
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#define I2C_SPI_SLV_RSR_TXDMABREQ_SET 0x00000008
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#define I2C_SPI_SLV_RSR_TXDMABREQ_CLR 0xfffffff7
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#define I2C_SPI_SLV_RSR_TXDMABREQ_MSB 3
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#define I2C_SPI_SLV_RSR_TXDMABREQ_LSB 3
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#define I2C_SPI_SLV_RSR_RXDMAPREQ_BITS 4:4
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#define I2C_SPI_SLV_RSR_RXDMAPREQ_SET 0x00000010
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#define I2C_SPI_SLV_RSR_RXDMAPREQ_CLR 0xffffffef
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#define I2C_SPI_SLV_RSR_RXDMAPREQ_MSB 4
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#define I2C_SPI_SLV_RSR_RXDMAPREQ_LSB 4
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#define I2C_SPI_SLV_RSR_RXDMABREQ_BITS 5:5
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#define I2C_SPI_SLV_RSR_RXDMABREQ_SET 0x00000020
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#define I2C_SPI_SLV_RSR_RXDMABREQ_CLR 0xffffffdf
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#define I2C_SPI_SLV_RSR_RXDMABREQ_MSB 5
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#define I2C_SPI_SLV_RSR_RXDMABREQ_LSB 5
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#define I2C_SPI_SLV_SLV HW_REGISTER_RW( 0x7e214008 )
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#define I2C_SPI_SLV_SLV_MASK 0x0000007f
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#define I2C_SPI_SLV_SLV_WIDTH 7
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#define I2C_SPI_SLV_SLV_RESET 0000000000
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#define I2C_SPI_SLV_SLV_ADDR_BITS 6:0
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#define I2C_SPI_SLV_SLV_ADDR_SET 0x0000007f
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#define I2C_SPI_SLV_SLV_ADDR_CLR 0xffffff80
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#define I2C_SPI_SLV_SLV_ADDR_MSB 6
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#define I2C_SPI_SLV_SLV_ADDR_LSB 0
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#define I2C_SPI_SLV_CR HW_REGISTER_RW( 0x7e21400c )
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#define I2C_SPI_SLV_CR_MASK 0x0001ffff
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#define I2C_SPI_SLV_CR_WIDTH 17
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#define I2C_SPI_SLV_CR_RESET 0000000000
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#define I2C_SPI_SLV_CR_EN_BITS 0:0
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#define I2C_SPI_SLV_CR_EN_SET 0x00000001
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#define I2C_SPI_SLV_CR_EN_CLR 0xfffffffe
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#define I2C_SPI_SLV_CR_EN_MSB 0
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#define I2C_SPI_SLV_CR_EN_LSB 0
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#define I2C_SPI_SLV_CR_SPI_BITS 1:1
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#define I2C_SPI_SLV_CR_SPI_SET 0x00000002
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#define I2C_SPI_SLV_CR_SPI_CLR 0xfffffffd
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#define I2C_SPI_SLV_CR_SPI_MSB 1
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#define I2C_SPI_SLV_CR_SPI_LSB 1
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#define I2C_SPI_SLV_CR_I2C_BITS 2:2
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#define I2C_SPI_SLV_CR_I2C_SET 0x00000004
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#define I2C_SPI_SLV_CR_I2C_CLR 0xfffffffb
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#define I2C_SPI_SLV_CR_I2C_MSB 2
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#define I2C_SPI_SLV_CR_I2C_LSB 2
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#define I2C_SPI_SLV_CR_CPHA_BITS 3:3
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#define I2C_SPI_SLV_CR_CPHA_SET 0x00000008
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#define I2C_SPI_SLV_CR_CPHA_CLR 0xfffffff7
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#define I2C_SPI_SLV_CR_CPHA_MSB 3
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#define I2C_SPI_SLV_CR_CPHA_LSB 3
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#define I2C_SPI_SLV_CR_CPOL_BITS 4:4
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#define I2C_SPI_SLV_CR_CPOL_SET 0x00000010
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#define I2C_SPI_SLV_CR_CPOL_CLR 0xffffffef
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#define I2C_SPI_SLV_CR_CPOL_MSB 4
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#define I2C_SPI_SLV_CR_CPOL_LSB 4
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#define I2C_SPI_SLV_CR_ENSTAT_BITS 5:5
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#define I2C_SPI_SLV_CR_ENSTAT_SET 0x00000020
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#define I2C_SPI_SLV_CR_ENSTAT_CLR 0xffffffdf
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#define I2C_SPI_SLV_CR_ENSTAT_MSB 5
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#define I2C_SPI_SLV_CR_ENSTAT_LSB 5
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#define I2C_SPI_SLV_CR_ENCTRL_BITS 6:6
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#define I2C_SPI_SLV_CR_ENCTRL_SET 0x00000040
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#define I2C_SPI_SLV_CR_ENCTRL_CLR 0xffffffbf
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#define I2C_SPI_SLV_CR_ENCTRL_MSB 6
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#define I2C_SPI_SLV_CR_ENCTRL_LSB 6
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#define I2C_SPI_SLV_CR_BRK_BITS 7:7
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#define I2C_SPI_SLV_CR_BRK_SET 0x00000080
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#define I2C_SPI_SLV_CR_BRK_CLR 0xffffff7f
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#define I2C_SPI_SLV_CR_BRK_MSB 7
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#define I2C_SPI_SLV_CR_BRK_LSB 7
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#define I2C_SPI_SLV_CR_TXE_BITS 8:8
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#define I2C_SPI_SLV_CR_TXE_SET 0x00000100
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#define I2C_SPI_SLV_CR_TXE_CLR 0xfffffeff
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#define I2C_SPI_SLV_CR_TXE_MSB 8
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#define I2C_SPI_SLV_CR_TXE_LSB 8
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#define I2C_SPI_SLV_CR_RXE_BITS 9:9
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#define I2C_SPI_SLV_CR_RXE_SET 0x00000200
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#define I2C_SPI_SLV_CR_RXE_CLR 0xfffffdff
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#define I2C_SPI_SLV_CR_RXE_MSB 9
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#define I2C_SPI_SLV_CR_RXE_LSB 9
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#define I2C_SPI_SLV_CR_INV_RXF_BITS 10:10
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#define I2C_SPI_SLV_CR_INV_RXF_SET 0x00000400
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#define I2C_SPI_SLV_CR_INV_RXF_CLR 0xfffffbff
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#define I2C_SPI_SLV_CR_INV_RXF_MSB 10
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#define I2C_SPI_SLV_CR_INV_RXF_LSB 10
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#define I2C_SPI_SLV_CR_TESTFIFO_BITS 11:11
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#define I2C_SPI_SLV_CR_TESTFIFO_SET 0x00000800
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#define I2C_SPI_SLV_CR_TESTFIFO_CLR 0xfffff7ff
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#define I2C_SPI_SLV_CR_TESTFIFO_MSB 11
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#define I2C_SPI_SLV_CR_TESTFIFO_LSB 11
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#define I2C_SPI_SLV_CR_HOSTCTRLEN_BITS 12:12
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#define I2C_SPI_SLV_CR_HOSTCTRLEN_SET 0x00001000
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#define I2C_SPI_SLV_CR_HOSTCTRLEN_CLR 0xffffefff
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#define I2C_SPI_SLV_CR_HOSTCTRLEN_MSB 12
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#define I2C_SPI_SLV_CR_HOSTCTRLEN_LSB 12
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#define I2C_SPI_SLV_CR_INV_TXF_BITS 13:13
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#define I2C_SPI_SLV_CR_INV_TXF_SET 0x00002000
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#define I2C_SPI_SLV_CR_INV_TXF_CLR 0xffffdfff
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#define I2C_SPI_SLV_CR_INV_TXF_MSB 13
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#define I2C_SPI_SLV_CR_INV_TXF_LSB 13
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#define I2C_SPI_SLV_FR HW_REGISTER_RW( 0x7e214010 )
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#define I2C_SPI_SLV_FR_MASK 0x0000ffff
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#define I2C_SPI_SLV_FR_WIDTH 16
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#define I2C_SPI_SLV_FR_RESET 0x00000012
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#define I2C_SPI_SLV_FR_TXBUSY_BITS 0:0
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#define I2C_SPI_SLV_FR_TXBUSY_SET 0x00000001
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#define I2C_SPI_SLV_FR_TXBUSY_CLR 0xfffffffe
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#define I2C_SPI_SLV_FR_TXBUSY_MSB 0
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#define I2C_SPI_SLV_FR_TXBUSY_LSB 0
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#define I2C_SPI_SLV_FR_RXFE_BITS 1:1
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#define I2C_SPI_SLV_FR_RXFE_SET 0x00000002
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#define I2C_SPI_SLV_FR_RXFE_CLR 0xfffffffd
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#define I2C_SPI_SLV_FR_RXFE_MSB 1
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#define I2C_SPI_SLV_FR_RXFE_LSB 1
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#define I2C_SPI_SLV_FR_TXFF_BITS 2:2
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#define I2C_SPI_SLV_FR_TXFF_SET 0x00000004
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#define I2C_SPI_SLV_FR_TXFF_CLR 0xfffffffb
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#define I2C_SPI_SLV_FR_TXFF_MSB 2
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#define I2C_SPI_SLV_FR_TXFF_LSB 2
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#define I2C_SPI_SLV_FR_RXFF_BITS 3:3
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#define I2C_SPI_SLV_FR_RXFF_SET 0x00000008
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#define I2C_SPI_SLV_FR_RXFF_CLR 0xfffffff7
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#define I2C_SPI_SLV_FR_RXFF_MSB 3
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#define I2C_SPI_SLV_FR_RXFF_LSB 3
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#define I2C_SPI_SLV_FR_TXFE_BITS 4:4
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#define I2C_SPI_SLV_FR_TXFE_SET 0x00000010
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#define I2C_SPI_SLV_FR_TXFE_CLR 0xffffffef
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#define I2C_SPI_SLV_FR_TXFE_MSB 4
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#define I2C_SPI_SLV_FR_TXFE_LSB 4
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#define I2C_SPI_SLV_FR_RXBUSY_BITS 5:5
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#define I2C_SPI_SLV_FR_RXBUSY_SET 0x00000020
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#define I2C_SPI_SLV_FR_RXBUSY_CLR 0xffffffdf
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#define I2C_SPI_SLV_FR_RXBUSY_MSB 5
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#define I2C_SPI_SLV_FR_RXBUSY_LSB 5
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#define I2C_SPI_SLV_FR_TXFLEVEL_BITS 6:10
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#define I2C_SPI_SLV_FR_TXFLEVEL_SET 0x00000000000
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#define I2C_SPI_SLV_FR_TXFLEVEL_CLR 0xffffffff111
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#define I2C_SPI_SLV_FR_TXFLEVEL_MSB 6
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#define I2C_SPI_SLV_FR_TXFLEVEL_LSB 10
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#define I2C_SPI_SLV_FR_RXFLEVEL_BITS 15:11
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#define I2C_SPI_SLV_FR_RXFLEVEL_SET 0x0000f800
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#define I2C_SPI_SLV_FR_RXFLEVEL_CLR 0xffff07ff
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#define I2C_SPI_SLV_FR_RXFLEVEL_MSB 15
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#define I2C_SPI_SLV_FR_RXFLEVEL_LSB 11
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#define I2C_SPI_SLV_IFLS HW_REGISTER_RW( 0x7e214014 )
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#define I2C_SPI_SLV_IFLS_MASK 0x00000fff
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#define I2C_SPI_SLV_IFLS_WIDTH 12
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#define I2C_SPI_SLV_IFLS_RESET 0x00000492
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#define I2C_SPI_SLV_IFLS_TXIFLSEL_BITS 2:0
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#define I2C_SPI_SLV_IFLS_TXIFLSEL_SET 0x00000007
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#define I2C_SPI_SLV_IFLS_TXIFLSEL_CLR 0xfffffff8
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#define I2C_SPI_SLV_IFLS_TXIFLSEL_MSB 2
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#define I2C_SPI_SLV_IFLS_TXIFLSEL_LSB 0
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#define I2C_SPI_SLV_IFLS_RXIFLSEL_BITS 5:3
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#define I2C_SPI_SLV_IFLS_RXIFLSEL_SET 0x00000038
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#define I2C_SPI_SLV_IFLS_RXIFLSEL_CLR 0xffffffc7
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#define I2C_SPI_SLV_IFLS_RXIFLSEL_MSB 5
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#define I2C_SPI_SLV_IFLS_RXIFLSEL_LSB 3
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#define I2C_SPI_SLV_IFLS_TXIFPSEL_BITS 8:6
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#define I2C_SPI_SLV_IFLS_TXIFPSEL_SET 0x000001c0
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#define I2C_SPI_SLV_IFLS_TXIFPSEL_CLR 0xfffffe3f
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#define I2C_SPI_SLV_IFLS_TXIFPSEL_MSB 8
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#define I2C_SPI_SLV_IFLS_TXIFPSEL_LSB 6
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#define I2C_SPI_SLV_IFLS_RXIFPSEL_BITS 11:9
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#define I2C_SPI_SLV_IFLS_RXIFPSEL_SET 0x00000e00
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#define I2C_SPI_SLV_IFLS_RXIFPSEL_CLR 0xfffff1ff
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#define I2C_SPI_SLV_IFLS_RXIFPSEL_MSB 11
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#define I2C_SPI_SLV_IFLS_RXIFPSEL_LSB 9
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#define I2C_SPI_SLV_IMSC HW_REGISTER_RW( 0x7e214018 )
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#define I2C_SPI_SLV_IMSC_MASK 0x0000000f
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#define I2C_SPI_SLV_IMSC_WIDTH 4
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#define I2C_SPI_SLV_IMSC_RESET 0000000000
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#define I2C_SPI_SLV_IMSC_RXIM_BITS 0:0
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#define I2C_SPI_SLV_IMSC_RXIM_SET 0x00000001
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#define I2C_SPI_SLV_IMSC_RXIM_CLR 0xfffffffe
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#define I2C_SPI_SLV_IMSC_RXIM_MSB 0
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#define I2C_SPI_SLV_IMSC_RXIM_LSB 0
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#define I2C_SPI_SLV_IMSC_TXIM_BITS 1:1
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#define I2C_SPI_SLV_IMSC_TXIM_SET 0x00000002
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#define I2C_SPI_SLV_IMSC_TXIM_CLR 0xfffffffd
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#define I2C_SPI_SLV_IMSC_TXIM_MSB 1
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#define I2C_SPI_SLV_IMSC_TXIM_LSB 1
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#define I2C_SPI_SLV_IMSC_BEIM_BITS 2:2
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#define I2C_SPI_SLV_IMSC_BEIM_SET 0x00000004
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#define I2C_SPI_SLV_IMSC_BEIM_CLR 0xfffffffb
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#define I2C_SPI_SLV_IMSC_BEIM_MSB 2
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#define I2C_SPI_SLV_IMSC_BEIM_LSB 2
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#define I2C_SPI_SLV_IMSC_OEIM_BITS 3:3
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#define I2C_SPI_SLV_IMSC_OEIM_SET 0x00000008
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#define I2C_SPI_SLV_IMSC_OEIM_CLR 0xfffffff7
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#define I2C_SPI_SLV_IMSC_OEIM_MSB 3
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#define I2C_SPI_SLV_IMSC_OEIM_LSB 3
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#define I2C_SPI_SLV_RIS HW_REGISTER_RW( 0x7e21401c )
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#define I2C_SPI_SLV_RIS_MASK 0x0000000f
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#define I2C_SPI_SLV_RIS_WIDTH 4
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#define I2C_SPI_SLV_RIS_RESET 0x00000002
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#define I2C_SPI_SLV_RIS_RXRIS_BITS 0:0
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#define I2C_SPI_SLV_RIS_RXRIS_SET 0x00000001
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#define I2C_SPI_SLV_RIS_RXRIS_CLR 0xfffffffe
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#define I2C_SPI_SLV_RIS_RXRIS_MSB 0
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#define I2C_SPI_SLV_RIS_RXRIS_LSB 0
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#define I2C_SPI_SLV_RIS_TXRIS_BITS 1:1
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#define I2C_SPI_SLV_RIS_TXRIS_SET 0x00000002
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#define I2C_SPI_SLV_RIS_TXRIS_CLR 0xfffffffd
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#define I2C_SPI_SLV_RIS_TXRIS_MSB 1
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#define I2C_SPI_SLV_RIS_TXRIS_LSB 1
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#define I2C_SPI_SLV_RIS_BERIS_BITS 2:2
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#define I2C_SPI_SLV_RIS_BERIS_SET 0x00000004
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#define I2C_SPI_SLV_RIS_BERIS_CLR 0xfffffffb
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#define I2C_SPI_SLV_RIS_BERIS_MSB 2
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#define I2C_SPI_SLV_RIS_BERIS_LSB 2
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#define I2C_SPI_SLV_RIS_OERIS_BITS 3:3
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#define I2C_SPI_SLV_RIS_OERIS_SET 0x00000008
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#define I2C_SPI_SLV_RIS_OERIS_CLR 0xfffffff7
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#define I2C_SPI_SLV_RIS_OERIS_MSB 3
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#define I2C_SPI_SLV_RIS_OERIS_LSB 3
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#define I2C_SPI_SLV_MIS HW_REGISTER_RW( 0x7e214020 )
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#define I2C_SPI_SLV_MIS_MASK 0x0000000f
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#define I2C_SPI_SLV_MIS_WIDTH 4
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#define I2C_SPI_SLV_MIS_RESET 0000000000
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#define I2C_SPI_SLV_MIS_RXMIS_BITS 0:0
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#define I2C_SPI_SLV_MIS_RXMIS_SET 0x00000001
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#define I2C_SPI_SLV_MIS_RXMIS_CLR 0xfffffffe
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#define I2C_SPI_SLV_MIS_RXMIS_MSB 0
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#define I2C_SPI_SLV_MIS_RXMIS_LSB 0
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#define I2C_SPI_SLV_MIS_TXMIS_BITS 1:1
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#define I2C_SPI_SLV_MIS_TXMIS_SET 0x00000002
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#define I2C_SPI_SLV_MIS_TXMIS_CLR 0xfffffffd
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#define I2C_SPI_SLV_MIS_TXMIS_MSB 1
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#define I2C_SPI_SLV_MIS_TXMIS_LSB 1
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#define I2C_SPI_SLV_MIS_BEMIS_BITS 2:2
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#define I2C_SPI_SLV_MIS_BEMIS_SET 0x00000004
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#define I2C_SPI_SLV_MIS_BEMIS_CLR 0xfffffffb
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#define I2C_SPI_SLV_MIS_BEMIS_MSB 2
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#define I2C_SPI_SLV_MIS_BEMIS_LSB 2
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#define I2C_SPI_SLV_MIS_OEMIS_BITS 3:3
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#define I2C_SPI_SLV_MIS_OEMIS_SET 0x00000008
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#define I2C_SPI_SLV_MIS_OEMIS_CLR 0xfffffff7
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#define I2C_SPI_SLV_MIS_OEMIS_MSB 3
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#define I2C_SPI_SLV_MIS_OEMIS_LSB 3
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#define I2C_SPI_SLV_ICR HW_REGISTER_RW( 0x7e214024 )
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#define I2C_SPI_SLV_ICR_MASK 0x0000000f
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#define I2C_SPI_SLV_ICR_WIDTH 4
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#define I2C_SPI_SLV_ICR_RESET 0000000000
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#define I2C_SPI_SLV_ICR_RXIC_BITS 0:0
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#define I2C_SPI_SLV_ICR_RXIC_SET 0x00000001
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#define I2C_SPI_SLV_ICR_RXIC_CLR 0xfffffffe
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#define I2C_SPI_SLV_ICR_RXIC_MSB 0
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#define I2C_SPI_SLV_ICR_RXIC_LSB 0
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#define I2C_SPI_SLV_ICR_TXIC_BITS 1:1
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#define I2C_SPI_SLV_ICR_TXIC_SET 0x00000002
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#define I2C_SPI_SLV_ICR_TXIC_CLR 0xfffffffd
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#define I2C_SPI_SLV_ICR_TXIC_MSB 1
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#define I2C_SPI_SLV_ICR_TXIC_LSB 1
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#define I2C_SPI_SLV_ICR_BEIC_BITS 2:2
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#define I2C_SPI_SLV_ICR_BEIC_SET 0x00000004
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#define I2C_SPI_SLV_ICR_BEIC_CLR 0xfffffffb
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#define I2C_SPI_SLV_ICR_BEIC_MSB 2
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#define I2C_SPI_SLV_ICR_BEIC_LSB 2
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#define I2C_SPI_SLV_ICR_OEIC_BITS 3:3
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#define I2C_SPI_SLV_ICR_OEIC_SET 0x00000008
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#define I2C_SPI_SLV_ICR_OEIC_CLR 0xfffffff7
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#define I2C_SPI_SLV_ICR_OEIC_MSB 3
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#define I2C_SPI_SLV_ICR_OEIC_LSB 3
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#define I2C_SPI_SLV_DMACR HW_REGISTER_RW( 0x7e214028 )
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#define I2C_SPI_SLV_DMACR_MASK 0x00000007
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#define I2C_SPI_SLV_DMACR_WIDTH 3
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#define I2C_SPI_SLV_DMACR_RESET 0000000000
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#define I2C_SPI_SLV_DMACR_RXDMAE_BITS 0:0
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#define I2C_SPI_SLV_DMACR_RXDMAE_SET 0x00000001
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#define I2C_SPI_SLV_DMACR_RXDMAE_CLR 0xfffffffe
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#define I2C_SPI_SLV_DMACR_RXDMAE_MSB 0
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#define I2C_SPI_SLV_DMACR_RXDMAE_LSB 0
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#define I2C_SPI_SLV_DMACR_TXDMAE_BITS 1:1
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#define I2C_SPI_SLV_DMACR_TXDMAE_SET 0x00000002
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#define I2C_SPI_SLV_DMACR_TXDMAE_CLR 0xfffffffd
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#define I2C_SPI_SLV_DMACR_TXDMAE_MSB 1
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#define I2C_SPI_SLV_DMACR_TXDMAE_LSB 1
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#define I2C_SPI_SLV_DMACR_DMAONERR_BITS 2:2
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#define I2C_SPI_SLV_DMACR_DMAONERR_SET 0x00000004
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#define I2C_SPI_SLV_DMACR_DMAONERR_CLR 0xfffffffb
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#define I2C_SPI_SLV_DMACR_DMAONERR_MSB 2
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#define I2C_SPI_SLV_DMACR_DMAONERR_LSB 2
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#define I2C_SPI_SLV_TDR HW_REGISTER_RW( 0x7e21402c )
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#define I2C_SPI_SLV_TDR_MASK 0x000000ff
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#define I2C_SPI_SLV_TDR_WIDTH 8
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#define I2C_SPI_SLV_TDR_RESET 0000000000
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#define I2C_SPI_SLV_TDR_DATA_BITS 7:0
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#define I2C_SPI_SLV_TDR_DATA_SET 0x000000ff
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#define I2C_SPI_SLV_TDR_DATA_CLR 0xffffff00
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#define I2C_SPI_SLV_TDR_DATA_MSB 7
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#define I2C_SPI_SLV_TDR_DATA_LSB 0
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#define I2C_SPI_SLV_VCSTAT HW_REGISTER_RW( 0x7e214030 )
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#define I2C_SPI_SLV_VCSTAT_MASK 0x0000000f
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#define I2C_SPI_SLV_VCSTAT_WIDTH 4
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#define I2C_SPI_SLV_VCSTAT_RESET 0000000000
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#define I2C_SPI_SLV_VCSTAT_DATA_BITS 3:0
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#define I2C_SPI_SLV_VCSTAT_DATA_SET 0x0000000f
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#define I2C_SPI_SLV_VCSTAT_DATA_CLR 0xfffffff0
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#define I2C_SPI_SLV_VCSTAT_DATA_MSB 3
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#define I2C_SPI_SLV_VCSTAT_DATA_LSB 0
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#define I2C_SPI_SLV_HCTRL HW_REGISTER_RW( 0x7e214034 )
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#define I2C_SPI_SLV_HCTRL_MASK 0x000000ff
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#define I2C_SPI_SLV_HCTRL_WIDTH 8
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#define I2C_SPI_SLV_HCTRL_RESET 0000000000
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#define I2C_SPI_SLV_HCTRL_DATA_BITS 7:0
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#define I2C_SPI_SLV_HCTRL_DATA_SET 0x000000ff
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#define I2C_SPI_SLV_HCTRL_DATA_CLR 0xffffff00
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#define I2C_SPI_SLV_HCTRL_DATA_MSB 7
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#define I2C_SPI_SLV_HCTRL_DATA_LSB 0
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#define I2C_SPI_SLV_DEBUG1 HW_REGISTER_RW( 0x7e214038 )
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#define I2C_SPI_SLV_DEBUG1_MASK 0x03ffffff
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#define I2C_SPI_SLV_DEBUG1_WIDTH 26
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#define I2C_SPI_SLV_DEBUG1_RESET 0x0000000e
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#define I2C_SPI_SLV_DEBUG1_DATA_BITS 25:0
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#define I2C_SPI_SLV_DEBUG1_DATA_SET 0x03ffffff
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#define I2C_SPI_SLV_DEBUG1_DATA_CLR 0xfc000000
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#define I2C_SPI_SLV_DEBUG1_DATA_MSB 25
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#define I2C_SPI_SLV_DEBUG1_DATA_LSB 0
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#define I2C_SPI_SLV_DEBUG2 HW_REGISTER_RW( 0x7e21403c )
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#define I2C_SPI_SLV_DEBUG2_MASK 0x00ffffff
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#define I2C_SPI_SLV_DEBUG2_WIDTH 24
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#define I2C_SPI_SLV_DEBUG2_RESET 0x00400000
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#define I2C_SPI_SLV_DEBUG2_DATA_BITS 23:0
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#define I2C_SPI_SLV_DEBUG2_DATA_SET 0x00ffffff
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#define I2C_SPI_SLV_DEBUG2_DATA_CLR 0xff000000
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#define I2C_SPI_SLV_DEBUG2_DATA_MSB 23
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#define I2C_SPI_SLV_DEBUG2_DATA_LSB 0
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