718 lines
50 KiB
C
Executable File
718 lines
50 KiB
C
Executable File
// This file was generated by the create_regs script
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#define MPHI_BASE 0x7e006000
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#define MPHI_APB_ID 0x6d706869
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#define MPHI_C0INDDA HW_REGISTER_RW( 0x7e006000 )
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#define MPHI_C0INDDA_MASK 0xffffffff
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#define MPHI_C0INDDA_WIDTH 32
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#define MPHI_C0INDDA_START_BITS 31:0
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#define MPHI_C0INDDA_START_SET 0xffffffff
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#define MPHI_C0INDDA_START_CLR 0x00000000
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#define MPHI_C0INDDA_START_MSB 31
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#define MPHI_C0INDDA_START_LSB 0
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#define MPHI_C0INDDA_START_RESET 0x0
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#define MPHI_C0INDDB HW_REGISTER_RW( 0x7e006004 )
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#define MPHI_C0INDDB_MASK 0xffffffff
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#define MPHI_C0INDDB_WIDTH 32
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#define MPHI_C0INDDB_MORUN_BITS 31:31
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#define MPHI_C0INDDB_MORUN_SET 0x80000000
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#define MPHI_C0INDDB_MORUN_CLR 0x7fffffff
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#define MPHI_C0INDDB_MORUN_MSB 31
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#define MPHI_C0INDDB_MORUN_LSB 31
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#define MPHI_C0INDDB_MORUN_RESET 0x0
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#define MPHI_C0INDDB_MENDINT_BITS 30:30
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#define MPHI_C0INDDB_MENDINT_SET 0x40000000
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#define MPHI_C0INDDB_MENDINT_CLR 0xbfffffff
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#define MPHI_C0INDDB_MENDINT_MSB 30
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#define MPHI_C0INDDB_MENDINT_LSB 30
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#define MPHI_C0INDDB_MENDINT_RESET 0x0
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#define MPHI_C0INDDB_TENDINT_BITS 29:29
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#define MPHI_C0INDDB_TENDINT_SET 0x20000000
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#define MPHI_C0INDDB_TENDINT_CLR 0xdfffffff
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#define MPHI_C0INDDB_TENDINT_MSB 29
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#define MPHI_C0INDDB_TENDINT_LSB 29
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#define MPHI_C0INDDB_TENDINT_RESET 0x0
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#define MPHI_C0INDDB_MTERM_BITS 28:28
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#define MPHI_C0INDDB_MTERM_SET 0x10000000
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#define MPHI_C0INDDB_MTERM_CLR 0xefffffff
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#define MPHI_C0INDDB_MTERM_MSB 28
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#define MPHI_C0INDDB_MTERM_LSB 28
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#define MPHI_C0INDDB_MTERM_RESET 0x0
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#define MPHI_C0INDDB_HANDLE_BITS 27:20
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#define MPHI_C0INDDB_HANDLE_SET 0x0ff00000
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#define MPHI_C0INDDB_HANDLE_CLR 0xf00fffff
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#define MPHI_C0INDDB_HANDLE_MSB 27
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#define MPHI_C0INDDB_HANDLE_LSB 20
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#define MPHI_C0INDDB_HANDLE_RESET 0x0
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#define MPHI_C0INDDB_LENGTH_BITS 19:0
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#define MPHI_C0INDDB_LENGTH_SET 0x000fffff
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#define MPHI_C0INDDB_LENGTH_CLR 0xfff00000
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#define MPHI_C0INDDB_LENGTH_MSB 19
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#define MPHI_C0INDDB_LENGTH_LSB 0
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#define MPHI_C0INDDB_LENGTH_RESET 0x0
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#define MPHI_C1INDDA HW_REGISTER_RW( 0x7e006008 )
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#define MPHI_C1INDDA_MASK 0xffffffff
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#define MPHI_C1INDDA_WIDTH 32
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#define MPHI_C1INDDA_START_BITS 31:0
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#define MPHI_C1INDDA_START_SET 0xffffffff
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#define MPHI_C1INDDA_START_CLR 0x00000000
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#define MPHI_C1INDDA_START_MSB 31
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#define MPHI_C1INDDA_START_LSB 0
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#define MPHI_C1INDDA_START_RESET 0x0
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#define MPHI_C1INDDB HW_REGISTER_RW( 0x7e00600c )
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#define MPHI_C1INDDB_MASK 0xffffffff
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#define MPHI_C1INDDB_WIDTH 32
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#define MPHI_C1INDDB_MORUN_BITS 31:31
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#define MPHI_C1INDDB_MORUN_SET 0x80000000
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#define MPHI_C1INDDB_MORUN_CLR 0x7fffffff
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#define MPHI_C1INDDB_MORUN_MSB 31
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#define MPHI_C1INDDB_MORUN_LSB 31
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#define MPHI_C1INDDB_MORUN_RESET 0x0
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#define MPHI_C1INDDB_MENDINT_BITS 30:30
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#define MPHI_C1INDDB_MENDINT_SET 0x40000000
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#define MPHI_C1INDDB_MENDINT_CLR 0xbfffffff
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#define MPHI_C1INDDB_MENDINT_MSB 30
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#define MPHI_C1INDDB_MENDINT_LSB 30
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#define MPHI_C1INDDB_MENDINT_RESET 0x0
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#define MPHI_C1INDDB_TENDINT_BITS 29:29
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#define MPHI_C1INDDB_TENDINT_SET 0x20000000
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#define MPHI_C1INDDB_TENDINT_CLR 0xdfffffff
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#define MPHI_C1INDDB_TENDINT_MSB 29
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#define MPHI_C1INDDB_TENDINT_LSB 29
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#define MPHI_C1INDDB_TENDINT_RESET 0x0
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#define MPHI_C1INDDB_MTERM_BITS 28:28
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#define MPHI_C1INDDB_MTERM_SET 0x10000000
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#define MPHI_C1INDDB_MTERM_CLR 0xefffffff
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#define MPHI_C1INDDB_MTERM_MSB 28
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#define MPHI_C1INDDB_MTERM_LSB 28
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#define MPHI_C1INDDB_MTERM_RESET 0x0
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#define MPHI_C1INDDB_HANDLE_BITS 27:20
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#define MPHI_C1INDDB_HANDLE_SET 0x0ff00000
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#define MPHI_C1INDDB_HANDLE_CLR 0xf00fffff
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#define MPHI_C1INDDB_HANDLE_MSB 27
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#define MPHI_C1INDDB_HANDLE_LSB 20
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#define MPHI_C1INDDB_HANDLE_RESET 0x0
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#define MPHI_C1INDDB_LENGTH_BITS 19:0
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#define MPHI_C1INDDB_LENGTH_SET 0x000fffff
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#define MPHI_C1INDDB_LENGTH_CLR 0xfff00000
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#define MPHI_C1INDDB_LENGTH_MSB 19
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#define MPHI_C1INDDB_LENGTH_LSB 0
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#define MPHI_C1INDDB_LENGTH_RESET 0x0
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#define MPHI_C0INDS HW_REGISTER_RW( 0x7e006010 )
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#define MPHI_C0INDS_MASK 0xdfffffff
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#define MPHI_C0INDS_WIDTH 32
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#define MPHI_C0INDS_DISCARD_BITS 31:31
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#define MPHI_C0INDS_DISCARD_SET 0x80000000
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#define MPHI_C0INDS_DISCARD_CLR 0x7fffffff
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#define MPHI_C0INDS_DISCARD_MSB 31
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#define MPHI_C0INDS_DISCARD_LSB 31
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#define MPHI_C0INDS_DISCARD_RESET 0x0
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#define MPHI_C0INDS_VALID_BITS 30:30
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#define MPHI_C0INDS_VALID_SET 0x40000000
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#define MPHI_C0INDS_VALID_CLR 0xbfffffff
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#define MPHI_C0INDS_VALID_MSB 30
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#define MPHI_C0INDS_VALID_LSB 30
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#define MPHI_C0INDS_VALID_RESET 0x0
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#define MPHI_C0INDS_HANDLE_BITS 28:21
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#define MPHI_C0INDS_HANDLE_SET 0x1fe00000
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#define MPHI_C0INDS_HANDLE_CLR 0xe01fffff
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#define MPHI_C0INDS_HANDLE_MSB 28
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#define MPHI_C0INDS_HANDLE_LSB 21
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#define MPHI_C0INDS_HANDLE_RESET 0x0
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#define MPHI_C0INDS_WORDS_BITS 20:0
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#define MPHI_C0INDS_WORDS_SET 0x001fffff
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#define MPHI_C0INDS_WORDS_CLR 0xffe00000
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#define MPHI_C0INDS_WORDS_MSB 20
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#define MPHI_C0INDS_WORDS_LSB 0
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#define MPHI_C0INDS_WORDS_RESET 0x0
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#define MPHI_C1INDS HW_REGISTER_RW( 0x7e006014 )
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#define MPHI_C1INDS_MASK 0xdfffffff
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#define MPHI_C1INDS_WIDTH 32
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#define MPHI_C1INDS_DISCARD_BITS 31:31
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#define MPHI_C1INDS_DISCARD_SET 0x80000000
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#define MPHI_C1INDS_DISCARD_CLR 0x7fffffff
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#define MPHI_C1INDS_DISCARD_MSB 31
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#define MPHI_C1INDS_DISCARD_LSB 31
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#define MPHI_C1INDS_DISCARD_RESET 0x0
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#define MPHI_C1INDS_VALID_BITS 30:30
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#define MPHI_C1INDS_VALID_SET 0x40000000
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#define MPHI_C1INDS_VALID_CLR 0xbfffffff
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#define MPHI_C1INDS_VALID_MSB 30
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#define MPHI_C1INDS_VALID_LSB 30
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#define MPHI_C1INDS_VALID_RESET 0x0
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#define MPHI_C1INDS_HANDLE_BITS 28:21
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#define MPHI_C1INDS_HANDLE_SET 0x1fe00000
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#define MPHI_C1INDS_HANDLE_CLR 0xe01fffff
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#define MPHI_C1INDS_HANDLE_MSB 28
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#define MPHI_C1INDS_HANDLE_LSB 21
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#define MPHI_C1INDS_HANDLE_RESET 0x0
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#define MPHI_C1INDS_WORDS_BITS 20:0
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#define MPHI_C1INDS_WORDS_SET 0x001fffff
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#define MPHI_C1INDS_WORDS_CLR 0xffe00000
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#define MPHI_C1INDS_WORDS_MSB 20
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#define MPHI_C1INDS_WORDS_LSB 0
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#define MPHI_C1INDS_WORDS_RESET 0x0
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#define MPHI_C0INDCF HW_REGISTER_RW( 0x7e006018 )
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#define MPHI_C0INDCF_MASK 0xffffffff
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#define MPHI_C0INDCF_WIDTH 32
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#define MPHI_C0INDCF_EMPTY_BITS 31:31
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#define MPHI_C0INDCF_EMPTY_SET 0x80000000
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#define MPHI_C0INDCF_EMPTY_CLR 0x7fffffff
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#define MPHI_C0INDCF_EMPTY_MSB 31
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#define MPHI_C0INDCF_EMPTY_LSB 31
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#define MPHI_C0INDCF_EMPTY_RESET 0x0
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#define MPHI_C0INDCF_LENERR_BITS 30:30
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#define MPHI_C0INDCF_LENERR_SET 0x40000000
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#define MPHI_C0INDCF_LENERR_CLR 0xbfffffff
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#define MPHI_C0INDCF_LENERR_MSB 30
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#define MPHI_C0INDCF_LENERR_LSB 30
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#define MPHI_C0INDCF_LENERR_RESET 0x0
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#define MPHI_C0INDCF_ORUN_BITS 29:29
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#define MPHI_C0INDCF_ORUN_SET 0x20000000
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#define MPHI_C0INDCF_ORUN_CLR 0xdfffffff
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#define MPHI_C0INDCF_ORUN_MSB 29
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#define MPHI_C0INDCF_ORUN_LSB 29
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#define MPHI_C0INDCF_ORUN_RESET 0x0
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#define MPHI_C0INDCF_MTERM_BITS 28:28
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#define MPHI_C0INDCF_MTERM_SET 0x10000000
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#define MPHI_C0INDCF_MTERM_CLR 0xefffffff
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#define MPHI_C0INDCF_MTERM_MSB 28
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#define MPHI_C0INDCF_MTERM_LSB 28
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#define MPHI_C0INDCF_MTERM_RESET 0x0
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#define MPHI_C0INDCF_HANDLE_BITS 27:20
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#define MPHI_C0INDCF_HANDLE_SET 0x0ff00000
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#define MPHI_C0INDCF_HANDLE_CLR 0xf00fffff
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#define MPHI_C0INDCF_HANDLE_MSB 27
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#define MPHI_C0INDCF_HANDLE_LSB 20
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#define MPHI_C0INDCF_HANDLE_RESET 0x0
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#define MPHI_C0INDCF_LENGTH_BITS 19:0
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#define MPHI_C0INDCF_LENGTH_SET 0x000fffff
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#define MPHI_C0INDCF_LENGTH_CLR 0xfff00000
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#define MPHI_C0INDCF_LENGTH_MSB 19
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#define MPHI_C0INDCF_LENGTH_LSB 0
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#define MPHI_C0INDCF_LENGTH_RESET 0x0
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#define MPHI_C1INDCF HW_REGISTER_RW( 0x7e00601c )
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#define MPHI_C1INDCF_MASK 0xffffffff
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#define MPHI_C1INDCF_WIDTH 32
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#define MPHI_C1INDCF_EMPTY_BITS 31:31
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#define MPHI_C1INDCF_EMPTY_SET 0x80000000
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#define MPHI_C1INDCF_EMPTY_CLR 0x7fffffff
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#define MPHI_C1INDCF_EMPTY_MSB 31
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#define MPHI_C1INDCF_EMPTY_LSB 31
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#define MPHI_C1INDCF_EMPTY_RESET 0x0
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#define MPHI_C1INDCF_LENERR_BITS 30:30
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#define MPHI_C1INDCF_LENERR_SET 0x40000000
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#define MPHI_C1INDCF_LENERR_CLR 0xbfffffff
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#define MPHI_C1INDCF_LENERR_MSB 30
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#define MPHI_C1INDCF_LENERR_LSB 30
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#define MPHI_C1INDCF_LENERR_RESET 0x0
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#define MPHI_C1INDCF_ORUN_BITS 29:29
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#define MPHI_C1INDCF_ORUN_SET 0x20000000
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#define MPHI_C1INDCF_ORUN_CLR 0xdfffffff
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#define MPHI_C1INDCF_ORUN_MSB 29
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#define MPHI_C1INDCF_ORUN_LSB 29
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#define MPHI_C1INDCF_ORUN_RESET 0x0
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#define MPHI_C1INDCF_MTERM_BITS 28:28
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#define MPHI_C1INDCF_MTERM_SET 0x10000000
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#define MPHI_C1INDCF_MTERM_CLR 0xefffffff
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#define MPHI_C1INDCF_MTERM_MSB 28
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#define MPHI_C1INDCF_MTERM_LSB 28
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#define MPHI_C1INDCF_MTERM_RESET 0x0
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#define MPHI_C1INDCF_HANDLE_BITS 27:20
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#define MPHI_C1INDCF_HANDLE_SET 0x0ff00000
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#define MPHI_C1INDCF_HANDLE_CLR 0xf00fffff
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#define MPHI_C1INDCF_HANDLE_MSB 27
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#define MPHI_C1INDCF_HANDLE_LSB 20
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#define MPHI_C1INDCF_HANDLE_RESET 0x0
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#define MPHI_C1INDCF_LENGTH_BITS 19:0
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#define MPHI_C1INDCF_LENGTH_SET 0x000fffff
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#define MPHI_C1INDCF_LENGTH_CLR 0xfff00000
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#define MPHI_C1INDCF_LENGTH_MSB 19
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#define MPHI_C1INDCF_LENGTH_LSB 0
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#define MPHI_C1INDCF_LENGTH_RESET 0x0
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#define MPHI_C0INDFS HW_REGISTER_RW( 0x7e006020 )
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#define MPHI_C0INDFS_MASK 0xffffffff
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#define MPHI_C0INDFS_WIDTH 32
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#define MPHI_C0INDFS_CFIFOLVL_BITS 31:16
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#define MPHI_C0INDFS_CFIFOLVL_SET 0xffff0000
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#define MPHI_C0INDFS_CFIFOLVL_CLR 0x0000ffff
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#define MPHI_C0INDFS_CFIFOLVL_MSB 31
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#define MPHI_C0INDFS_CFIFOLVL_LSB 16
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#define MPHI_C0INDFS_CFIFOLVL_RESET 0x0
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#define MPHI_C0INDFS_DFIFOLVL_BITS 15:0
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#define MPHI_C0INDFS_DFIFOLVL_SET 0x0000ffff
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#define MPHI_C0INDFS_DFIFOLVL_CLR 0xffff0000
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#define MPHI_C0INDFS_DFIFOLVL_MSB 15
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#define MPHI_C0INDFS_DFIFOLVL_LSB 0
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#define MPHI_C0INDFS_DFIFOLVL_RESET 0x0
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#define MPHI_C1INDFS HW_REGISTER_RW( 0x7e006024 )
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#define MPHI_C1INDFS_MASK 0xffffffff
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#define MPHI_C1INDFS_WIDTH 32
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#define MPHI_C1INDFS_CFIFOLVL_BITS 31:16
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#define MPHI_C1INDFS_CFIFOLVL_SET 0xffff0000
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#define MPHI_C1INDFS_CFIFOLVL_CLR 0x0000ffff
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#define MPHI_C1INDFS_CFIFOLVL_MSB 31
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#define MPHI_C1INDFS_CFIFOLVL_LSB 16
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#define MPHI_C1INDFS_CFIFOLVL_RESET 0x0
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#define MPHI_C1INDFS_DFIFOLVL_BITS 15:0
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#define MPHI_C1INDFS_DFIFOLVL_SET 0x0000ffff
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#define MPHI_C1INDFS_DFIFOLVL_CLR 0xffff0000
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#define MPHI_C1INDFS_DFIFOLVL_MSB 15
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#define MPHI_C1INDFS_DFIFOLVL_LSB 0
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#define MPHI_C1INDFS_DFIFOLVL_RESET 0x0
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#define MPHI_OUTDDA HW_REGISTER_RW( 0x7e006028 )
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#define MPHI_OUTDDA_MASK 0xffffffff
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#define MPHI_OUTDDA_WIDTH 32
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#define MPHI_OUTDDA_START_BITS 31:0
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#define MPHI_OUTDDA_START_SET 0xffffffff
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#define MPHI_OUTDDA_START_CLR 0x00000000
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#define MPHI_OUTDDA_START_MSB 31
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#define MPHI_OUTDDA_START_LSB 0
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#define MPHI_OUTDDA_START_RESET 0x0
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#define MPHI_OUTDDB HW_REGISTER_RW( 0x7e00602c )
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#define MPHI_OUTDDB_MASK 0x3fffffff
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#define MPHI_OUTDDB_WIDTH 30
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#define MPHI_OUTDDB_TENDINT_BITS 29:29
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#define MPHI_OUTDDB_TENDINT_SET 0x20000000
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#define MPHI_OUTDDB_TENDINT_CLR 0xdfffffff
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#define MPHI_OUTDDB_TENDINT_MSB 29
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#define MPHI_OUTDDB_TENDINT_LSB 29
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#define MPHI_OUTDDB_TENDINT_RESET 0x0
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#define MPHI_OUTDDB_CHANNEL_BITS 28:28
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#define MPHI_OUTDDB_CHANNEL_SET 0x10000000
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#define MPHI_OUTDDB_CHANNEL_CLR 0xefffffff
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#define MPHI_OUTDDB_CHANNEL_MSB 28
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#define MPHI_OUTDDB_CHANNEL_LSB 28
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#define MPHI_OUTDDB_CHANNEL_RESET 0x0
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#define MPHI_OUTDDB_HANDLE_BITS 27:20
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#define MPHI_OUTDDB_HANDLE_SET 0x0ff00000
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#define MPHI_OUTDDB_HANDLE_CLR 0xf00fffff
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#define MPHI_OUTDDB_HANDLE_MSB 27
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#define MPHI_OUTDDB_HANDLE_LSB 20
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#define MPHI_OUTDDB_HANDLE_RESET 0x0
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#define MPHI_OUTDDB_LENGTH_BITS 19:0
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#define MPHI_OUTDDB_LENGTH_SET 0x000fffff
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#define MPHI_OUTDDB_LENGTH_CLR 0xfff00000
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#define MPHI_OUTDDB_LENGTH_MSB 19
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#define MPHI_OUTDDB_LENGTH_LSB 0
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#define MPHI_OUTDDB_LENGTH_RESET 0x0
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#define MPHI_OUTDS HW_REGISTER_RW( 0x7e006030 )
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#define MPHI_OUTDS_MASK 0x5fffffff
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#define MPHI_OUTDS_WIDTH 31
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#define MPHI_OUTDS_VALID_BITS 30:30
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#define MPHI_OUTDS_VALID_SET 0x40000000
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#define MPHI_OUTDS_VALID_CLR 0xbfffffff
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#define MPHI_OUTDS_VALID_MSB 30
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#define MPHI_OUTDS_VALID_LSB 30
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#define MPHI_OUTDS_VALID_RESET 0x0
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#define MPHI_OUTDS_HANDLE_BITS 28:21
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#define MPHI_OUTDS_HANDLE_SET 0x1fe00000
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#define MPHI_OUTDS_HANDLE_CLR 0xe01fffff
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#define MPHI_OUTDS_HANDLE_MSB 28
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#define MPHI_OUTDS_HANDLE_LSB 21
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#define MPHI_OUTDS_HANDLE_RESET 0x0
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#define MPHI_OUTDS_WORDS_BITS 20:0
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#define MPHI_OUTDS_WORDS_SET 0x001fffff
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#define MPHI_OUTDS_WORDS_CLR 0xffe00000
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#define MPHI_OUTDS_WORDS_MSB 20
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#define MPHI_OUTDS_WORDS_LSB 0
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#define MPHI_OUTDS_WORDS_RESET 0x0
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#define MPHI_OUTDFS HW_REGISTER_RW( 0x7e006034 )
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#define MPHI_OUTDFS_MASK 0xffffffff
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#define MPHI_OUTDFS_WIDTH 32
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#define MPHI_OUTDFS_DFIFOLVL_BITS 15:0
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#define MPHI_OUTDFS_DFIFOLVL_SET 0x0000ffff
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#define MPHI_OUTDFS_DFIFOLVL_CLR 0xffff0000
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#define MPHI_OUTDFS_DFIFOLVL_MSB 15
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#define MPHI_OUTDFS_DFIFOLVL_LSB 0
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#define MPHI_OUTDFS_DFIFOLVL_RESET 0x0
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#define MPHI_MINFS HW_REGISTER_RW( 0x7e006038 )
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#define MPHI_MINFS_MASK 0xbfffffff
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#define MPHI_MINFS_WIDTH 32
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#define MPHI_MINFS_OFLOW_BITS 31:31
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#define MPHI_MINFS_OFLOW_SET 0x80000000
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#define MPHI_MINFS_OFLOW_CLR 0x7fffffff
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#define MPHI_MINFS_OFLOW_MSB 31
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#define MPHI_MINFS_OFLOW_LSB 31
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#define MPHI_MINFS_OFLOW_RESET 0x0
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#define MPHI_MINFS_RPTR_BITS 29:20
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#define MPHI_MINFS_RPTR_SET 0x3ff00000
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#define MPHI_MINFS_RPTR_CLR 0xc00fffff
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#define MPHI_MINFS_RPTR_MSB 29
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#define MPHI_MINFS_RPTR_LSB 20
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#define MPHI_MINFS_RPTR_RESET 0x0
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#define MPHI_MINFS_WPTR_BITS 19:10
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#define MPHI_MINFS_WPTR_SET 0x000ffc00
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#define MPHI_MINFS_WPTR_CLR 0xfff003ff
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#define MPHI_MINFS_WPTR_MSB 19
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#define MPHI_MINFS_WPTR_LSB 10
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#define MPHI_MINFS_WPTR_RESET 0x0
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#define MPHI_MINFS_LEVEL_BITS 9:0
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#define MPHI_MINFS_LEVEL_SET 0x000003ff
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#define MPHI_MINFS_LEVEL_CLR 0xfffffc00
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#define MPHI_MINFS_LEVEL_MSB 9
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#define MPHI_MINFS_LEVEL_LSB 0
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#define MPHI_MINFS_LEVEL_RESET 0x0
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#define MPHI_MOUTFS HW_REGISTER_RW( 0x7e00603c )
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#define MPHI_MOUTFS_MASK 0xbfffffff
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#define MPHI_MOUTFS_WIDTH 32
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#define MPHI_MOUTFS_UFLOW_BITS 31:31
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#define MPHI_MOUTFS_UFLOW_SET 0x80000000
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#define MPHI_MOUTFS_UFLOW_CLR 0x7fffffff
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#define MPHI_MOUTFS_UFLOW_MSB 31
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#define MPHI_MOUTFS_UFLOW_LSB 31
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#define MPHI_MOUTFS_UFLOW_RESET 0x0
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#define MPHI_MOUTFS_RPTR_BITS 29:20
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#define MPHI_MOUTFS_RPTR_SET 0x3ff00000
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#define MPHI_MOUTFS_RPTR_CLR 0xc00fffff
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#define MPHI_MOUTFS_RPTR_MSB 29
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#define MPHI_MOUTFS_RPTR_LSB 20
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#define MPHI_MOUTFS_RPTR_RESET 0x0
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#define MPHI_MOUTFS_WPTR_BITS 19:10
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#define MPHI_MOUTFS_WPTR_SET 0x000ffc00
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#define MPHI_MOUTFS_WPTR_CLR 0xfff003ff
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#define MPHI_MOUTFS_WPTR_MSB 19
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#define MPHI_MOUTFS_WPTR_LSB 10
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#define MPHI_MOUTFS_WPTR_RESET 0x0
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#define MPHI_MOUTFS_LEVEL_BITS 9:0
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#define MPHI_MOUTFS_LEVEL_SET 0x000003ff
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#define MPHI_MOUTFS_LEVEL_CLR 0xfffffc00
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#define MPHI_MOUTFS_LEVEL_MSB 9
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#define MPHI_MOUTFS_LEVEL_LSB 0
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#define MPHI_MOUTFS_LEVEL_RESET 0x0
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#define MPHI_AXIPRIV HW_REGISTER_RW( 0x7e006040 )
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#define MPHI_AXIPRIV_MASK 0x00000177
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#define MPHI_AXIPRIV_WIDTH 9
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#define MPHI_AXIPRIV_HSPECEN_BITS 8:8
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#define MPHI_AXIPRIV_HSPECEN_SET 0x00000100
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#define MPHI_AXIPRIV_HSPECEN_CLR 0xfffffeff
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#define MPHI_AXIPRIV_HSPECEN_MSB 8
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#define MPHI_AXIPRIV_HSPECEN_LSB 8
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#define MPHI_AXIPRIV_HSPECEN_RESET 0x0
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#define MPHI_AXIPRIV_RXPROT_BITS 6:4
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#define MPHI_AXIPRIV_RXPROT_SET 0x00000070
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#define MPHI_AXIPRIV_RXPROT_CLR 0xffffff8f
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#define MPHI_AXIPRIV_RXPROT_MSB 6
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#define MPHI_AXIPRIV_RXPROT_LSB 4
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#define MPHI_AXIPRIV_RXPROT_RESET 0x2
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#define MPHI_AXIPRIV_TXPROT_BITS 2:0
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#define MPHI_AXIPRIV_TXPROT_SET 0x00000007
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#define MPHI_AXIPRIV_TXPROT_CLR 0xfffffff8
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#define MPHI_AXIPRIV_TXPROT_MSB 2
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#define MPHI_AXIPRIV_TXPROT_LSB 0
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#define MPHI_AXIPRIV_TXPROT_RESET 0x2
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#define MPHI_RXAXICFG HW_REGISTER_RW( 0x7e006044 )
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#define MPHI_RXAXICFG_MASK 0x0001ffff
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#define MPHI_RXAXICFG_WIDTH 17
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#define MPHI_RXAXICFG_INTHRESH_BITS 16:8
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#define MPHI_RXAXICFG_INTHRESH_SET 0x0001ff00
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#define MPHI_RXAXICFG_INTHRESH_CLR 0xfffe00ff
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#define MPHI_RXAXICFG_INTHRESH_MSB 16
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#define MPHI_RXAXICFG_INTHRESH_LSB 8
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#define MPHI_RXAXICFG_INTHRESH_RESET 0x0
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#define MPHI_RXAXICFG_RXPPRIO_BITS 7:4
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#define MPHI_RXAXICFG_RXPPRIO_SET 0x000000f0
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#define MPHI_RXAXICFG_RXPPRIO_CLR 0xffffff0f
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#define MPHI_RXAXICFG_RXPPRIO_MSB 7
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#define MPHI_RXAXICFG_RXPPRIO_LSB 4
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#define MPHI_RXAXICFG_RXPPRIO_RESET 0x0
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#define MPHI_RXAXICFG_RXNPRIO_BITS 3:0
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#define MPHI_RXAXICFG_RXNPRIO_SET 0x0000000f
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#define MPHI_RXAXICFG_RXNPRIO_CLR 0xfffffff0
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#define MPHI_RXAXICFG_RXNPRIO_MSB 3
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#define MPHI_RXAXICFG_RXNPRIO_LSB 0
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#define MPHI_RXAXICFG_RXNPRIO_RESET 0x0
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#define MPHI_TXAXICFG HW_REGISTER_RW( 0x7e006048 )
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#define MPHI_TXAXICFG_MASK 0x0001ffff
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#define MPHI_TXAXICFG_WIDTH 17
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#define MPHI_TXAXICFG_INTHRESH_BITS 16:8
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#define MPHI_TXAXICFG_INTHRESH_SET 0x0001ff00
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#define MPHI_TXAXICFG_INTHRESH_CLR 0xfffe00ff
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#define MPHI_TXAXICFG_INTHRESH_MSB 16
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#define MPHI_TXAXICFG_INTHRESH_LSB 8
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#define MPHI_TXAXICFG_INTHRESH_RESET 0x0
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#define MPHI_TXAXICFG_TXPPRIO_BITS 7:4
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#define MPHI_TXAXICFG_TXPPRIO_SET 0x000000f0
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#define MPHI_TXAXICFG_TXPPRIO_CLR 0xffffff0f
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#define MPHI_TXAXICFG_TXPPRIO_MSB 7
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#define MPHI_TXAXICFG_TXPPRIO_LSB 4
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#define MPHI_TXAXICFG_TXPPRIO_RESET 0x0
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#define MPHI_TXAXICFG_TXNPRIO_BITS 3:0
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#define MPHI_TXAXICFG_TXNPRIO_SET 0x0000000f
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#define MPHI_TXAXICFG_TXNPRIO_CLR 0xfffffff0
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#define MPHI_TXAXICFG_TXNPRIO_MSB 3
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#define MPHI_TXAXICFG_TXNPRIO_LSB 0
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#define MPHI_TXAXICFG_TXNPRIO_RESET 0x0
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#define MPHI_CTRL HW_REGISTER_RW( 0x7e00604c )
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#define MPHI_CTRL_MASK 0x88031111
|
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#define MPHI_CTRL_WIDTH 32
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#define MPHI_CTRL_ENABLE_BITS 31:31
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#define MPHI_CTRL_ENABLE_SET 0x80000000
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#define MPHI_CTRL_ENABLE_CLR 0x7fffffff
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#define MPHI_CTRL_ENABLE_MSB 31
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#define MPHI_CTRL_ENABLE_LSB 31
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#define MPHI_CTRL_ENABLE_RESET 0x0
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#define MPHI_CTRL_STBY_BITS 27:27
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#define MPHI_CTRL_STBY_SET 0x08000000
|
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#define MPHI_CTRL_STBY_CLR 0xf7ffffff
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#define MPHI_CTRL_STBY_MSB 27
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#define MPHI_CTRL_STBY_LSB 27
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#define MPHI_CTRL_STBY_RESET 0x1
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#define MPHI_CTRL_SOFT_RST_DNE_BITS 17:17
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#define MPHI_CTRL_SOFT_RST_DNE_SET 0x00020000
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#define MPHI_CTRL_SOFT_RST_DNE_CLR 0xfffdffff
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#define MPHI_CTRL_SOFT_RST_DNE_MSB 17
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#define MPHI_CTRL_SOFT_RST_DNE_LSB 17
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#define MPHI_CTRL_SOFT_RST_DNE_RESET 0x0
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#define MPHI_CTRL_REQ_SOFT_RST_BITS 16:16
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#define MPHI_CTRL_REQ_SOFT_RST_SET 0x00010000
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#define MPHI_CTRL_REQ_SOFT_RST_CLR 0xfffeffff
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#define MPHI_CTRL_REQ_SOFT_RST_MSB 16
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#define MPHI_CTRL_REQ_SOFT_RST_LSB 16
|
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#define MPHI_CTRL_REQ_SOFT_RST_RESET 0x0
|
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#define MPHI_CTRL_EIGHTBIT_BITS 12:12
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#define MPHI_CTRL_EIGHTBIT_SET 0x00001000
|
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#define MPHI_CTRL_EIGHTBIT_CLR 0xffffefff
|
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#define MPHI_CTRL_EIGHTBIT_MSB 12
|
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#define MPHI_CTRL_EIGHTBIT_LSB 12
|
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#define MPHI_CTRL_EIGHTBIT_RESET 0x1
|
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#define MPHI_CTRL_INVERT_BITS 8:8
|
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#define MPHI_CTRL_INVERT_SET 0x00000100
|
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#define MPHI_CTRL_INVERT_CLR 0xfffffeff
|
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#define MPHI_CTRL_INVERT_MSB 8
|
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#define MPHI_CTRL_INVERT_LSB 8
|
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#define MPHI_CTRL_INVERT_RESET 0x0
|
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#define MPHI_CTRL_DIRECT_BITS 4:4
|
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#define MPHI_CTRL_DIRECT_SET 0x00000010
|
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#define MPHI_CTRL_DIRECT_CLR 0xffffffef
|
|
#define MPHI_CTRL_DIRECT_MSB 4
|
|
#define MPHI_CTRL_DIRECT_LSB 4
|
|
#define MPHI_CTRL_DIRECT_RESET 0x0
|
|
#define MPHI_CTRL_HATVAL_BITS 0:0
|
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#define MPHI_CTRL_HATVAL_SET 0x00000001
|
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#define MPHI_CTRL_HATVAL_CLR 0xfffffffe
|
|
#define MPHI_CTRL_HATVAL_MSB 0
|
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#define MPHI_CTRL_HATVAL_LSB 0
|
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#define MPHI_CTRL_HATVAL_RESET 0x0
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#define MPHI_INTSTAT HW_REGISTER_RW( 0x7e006050 )
|
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#define MPHI_INTSTAT_MASK 0xf9111111
|
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#define MPHI_INTSTAT_WIDTH 32
|
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#define MPHI_INTSTAT_HSTEND_BITS 31:31
|
|
#define MPHI_INTSTAT_HSTEND_SET 0x80000000
|
|
#define MPHI_INTSTAT_HSTEND_CLR 0x7fffffff
|
|
#define MPHI_INTSTAT_HSTEND_MSB 31
|
|
#define MPHI_INTSTAT_HSTEND_LSB 31
|
|
#define MPHI_INTSTAT_HSTEND_RESET 0x0
|
|
#define MPHI_INTSTAT_HSDISC_BITS 30:30
|
|
#define MPHI_INTSTAT_HSDISC_SET 0x40000000
|
|
#define MPHI_INTSTAT_HSDISC_CLR 0xbfffffff
|
|
#define MPHI_INTSTAT_HSDISC_MSB 30
|
|
#define MPHI_INTSTAT_HSDISC_LSB 30
|
|
#define MPHI_INTSTAT_HSDISC_RESET 0x0
|
|
#define MPHI_INTSTAT_IMFOFLW_BITS 29:29
|
|
#define MPHI_INTSTAT_IMFOFLW_SET 0x20000000
|
|
#define MPHI_INTSTAT_IMFOFLW_CLR 0xdfffffff
|
|
#define MPHI_INTSTAT_IMFOFLW_MSB 29
|
|
#define MPHI_INTSTAT_IMFOFLW_LSB 29
|
|
#define MPHI_INTSTAT_IMFOFLW_RESET 0x0
|
|
#define MPHI_INTSTAT_OMFUFLW_BITS 28:28
|
|
#define MPHI_INTSTAT_OMFUFLW_SET 0x10000000
|
|
#define MPHI_INTSTAT_OMFUFLW_CLR 0xefffffff
|
|
#define MPHI_INTSTAT_OMFUFLW_MSB 28
|
|
#define MPHI_INTSTAT_OMFUFLW_LSB 28
|
|
#define MPHI_INTSTAT_OMFUFLW_RESET 0x0
|
|
#define MPHI_INTSTAT_HSDCFOFLW_BITS 27:27
|
|
#define MPHI_INTSTAT_HSDCFOFLW_SET 0x08000000
|
|
#define MPHI_INTSTAT_HSDCFOFLW_CLR 0xf7ffffff
|
|
#define MPHI_INTSTAT_HSDCFOFLW_MSB 27
|
|
#define MPHI_INTSTAT_HSDCFOFLW_LSB 27
|
|
#define MPHI_INTSTAT_HSDCFOFLW_RESET 0x0
|
|
#define MPHI_INTSTAT_RX1DISC_BITS 24:24
|
|
#define MPHI_INTSTAT_RX1DISC_SET 0x01000000
|
|
#define MPHI_INTSTAT_RX1DISC_CLR 0xfeffffff
|
|
#define MPHI_INTSTAT_RX1DISC_MSB 24
|
|
#define MPHI_INTSTAT_RX1DISC_LSB 24
|
|
#define MPHI_INTSTAT_RX1DISC_RESET 0x0
|
|
#define MPHI_INTSTAT_RX0DISC_BITS 20:20
|
|
#define MPHI_INTSTAT_RX0DISC_SET 0x00100000
|
|
#define MPHI_INTSTAT_RX0DISC_CLR 0xffefffff
|
|
#define MPHI_INTSTAT_RX0DISC_MSB 20
|
|
#define MPHI_INTSTAT_RX0DISC_LSB 20
|
|
#define MPHI_INTSTAT_RX0DISC_RESET 0x0
|
|
#define MPHI_INTSTAT_TXEND_BITS 16:16
|
|
#define MPHI_INTSTAT_TXEND_SET 0x00010000
|
|
#define MPHI_INTSTAT_TXEND_CLR 0xfffeffff
|
|
#define MPHI_INTSTAT_TXEND_MSB 16
|
|
#define MPHI_INTSTAT_TXEND_LSB 16
|
|
#define MPHI_INTSTAT_TXEND_RESET 0x0
|
|
#define MPHI_INTSTAT_RX1TEND_BITS 12:12
|
|
#define MPHI_INTSTAT_RX1TEND_SET 0x00001000
|
|
#define MPHI_INTSTAT_RX1TEND_CLR 0xffffefff
|
|
#define MPHI_INTSTAT_RX1TEND_MSB 12
|
|
#define MPHI_INTSTAT_RX1TEND_LSB 12
|
|
#define MPHI_INTSTAT_RX1TEND_RESET 0x0
|
|
#define MPHI_INTSTAT_RX1MEND_BITS 8:8
|
|
#define MPHI_INTSTAT_RX1MEND_SET 0x00000100
|
|
#define MPHI_INTSTAT_RX1MEND_CLR 0xfffffeff
|
|
#define MPHI_INTSTAT_RX1MEND_MSB 8
|
|
#define MPHI_INTSTAT_RX1MEND_LSB 8
|
|
#define MPHI_INTSTAT_RX1MEND_RESET 0x0
|
|
#define MPHI_INTSTAT_RX0TEND_BITS 4:4
|
|
#define MPHI_INTSTAT_RX0TEND_SET 0x00000010
|
|
#define MPHI_INTSTAT_RX0TEND_CLR 0xffffffef
|
|
#define MPHI_INTSTAT_RX0TEND_MSB 4
|
|
#define MPHI_INTSTAT_RX0TEND_LSB 4
|
|
#define MPHI_INTSTAT_RX0TEND_RESET 0x0
|
|
#define MPHI_INTSTAT_RX0MEND_BITS 0:0
|
|
#define MPHI_INTSTAT_RX0MEND_SET 0x00000001
|
|
#define MPHI_INTSTAT_RX0MEND_CLR 0xfffffffe
|
|
#define MPHI_INTSTAT_RX0MEND_MSB 0
|
|
#define MPHI_INTSTAT_RX0MEND_LSB 0
|
|
#define MPHI_INTSTAT_RX0MEND_RESET 0x0
|
|
#define MPHI_VERSION HW_REGISTER_RO( 0x7e006054 )
|
|
#define MPHI_VERSION_MASK 0xffffffff
|
|
#define MPHI_VERSION_WIDTH 32
|
|
#define MPHI_INTCTRL HW_REGISTER_RW( 0x7e006058 )
|
|
#define MPHI_INTCTRL_MASK 0x00111111
|
|
#define MPHI_INTCTRL_WIDTH 21
|
|
#define MPHI_INTCTRL_HSDCOFLW_BITS 20:20
|
|
#define MPHI_INTCTRL_HSDCOFLW_SET 0x00100000
|
|
#define MPHI_INTCTRL_HSDCOFLW_CLR 0xffefffff
|
|
#define MPHI_INTCTRL_HSDCOFLW_MSB 20
|
|
#define MPHI_INTCTRL_HSDCOFLW_LSB 20
|
|
#define MPHI_INTCTRL_HSDCOFLW_RESET 0x0
|
|
#define MPHI_INTCTRL_HSDISC_BITS 16:16
|
|
#define MPHI_INTCTRL_HSDISC_SET 0x00010000
|
|
#define MPHI_INTCTRL_HSDISC_CLR 0xfffeffff
|
|
#define MPHI_INTCTRL_HSDISC_MSB 16
|
|
#define MPHI_INTCTRL_HSDISC_LSB 16
|
|
#define MPHI_INTCTRL_HSDISC_RESET 0x0
|
|
#define MPHI_INTCTRL_OMFUFLW_BITS 12:12
|
|
#define MPHI_INTCTRL_OMFUFLW_SET 0x00001000
|
|
#define MPHI_INTCTRL_OMFUFLW_CLR 0xffffefff
|
|
#define MPHI_INTCTRL_OMFUFLW_MSB 12
|
|
#define MPHI_INTCTRL_OMFUFLW_LSB 12
|
|
#define MPHI_INTCTRL_OMFUFLW_RESET 0x0
|
|
#define MPHI_INTCTRL_IMFOFLW_BITS 8:8
|
|
#define MPHI_INTCTRL_IMFOFLW_SET 0x00000100
|
|
#define MPHI_INTCTRL_IMFOFLW_CLR 0xfffffeff
|
|
#define MPHI_INTCTRL_IMFOFLW_MSB 8
|
|
#define MPHI_INTCTRL_IMFOFLW_LSB 8
|
|
#define MPHI_INTCTRL_IMFOFLW_RESET 0x0
|
|
#define MPHI_INTCTRL_RX1DISC_BITS 4:4
|
|
#define MPHI_INTCTRL_RX1DISC_SET 0x00000010
|
|
#define MPHI_INTCTRL_RX1DISC_CLR 0xffffffef
|
|
#define MPHI_INTCTRL_RX1DISC_MSB 4
|
|
#define MPHI_INTCTRL_RX1DISC_LSB 4
|
|
#define MPHI_INTCTRL_RX1DISC_RESET 0x0
|
|
#define MPHI_INTCTRL_RX0DISC_BITS 0:0
|
|
#define MPHI_INTCTRL_RX0DISC_SET 0x00000001
|
|
#define MPHI_INTCTRL_RX0DISC_CLR 0xfffffffe
|
|
#define MPHI_INTCTRL_RX0DISC_MSB 0
|
|
#define MPHI_INTCTRL_RX0DISC_LSB 0
|
|
#define MPHI_INTCTRL_RX0DISC_RESET 0x0
|
|
#define MPHI_HSINDCF HW_REGISTER_RW( 0x7e00605c )
|
|
#define MPHI_HSINDCF_MASK 0xdfffffff
|
|
#define MPHI_HSINDCF_WIDTH 32
|
|
#define MPHI_HSINDCF_EMPTY_BITS 31:31
|
|
#define MPHI_HSINDCF_EMPTY_SET 0x80000000
|
|
#define MPHI_HSINDCF_EMPTY_CLR 0x7fffffff
|
|
#define MPHI_HSINDCF_EMPTY_MSB 31
|
|
#define MPHI_HSINDCF_EMPTY_LSB 31
|
|
#define MPHI_HSINDCF_EMPTY_RESET 0x0
|
|
#define MPHI_HSINDCF_LENERR_BITS 30:30
|
|
#define MPHI_HSINDCF_LENERR_SET 0x40000000
|
|
#define MPHI_HSINDCF_LENERR_CLR 0xbfffffff
|
|
#define MPHI_HSINDCF_LENERR_MSB 30
|
|
#define MPHI_HSINDCF_LENERR_LSB 30
|
|
#define MPHI_HSINDCF_LENERR_RESET 0x0
|
|
#define MPHI_HSINDCF_MTERM_BITS 28:28
|
|
#define MPHI_HSINDCF_MTERM_SET 0x10000000
|
|
#define MPHI_HSINDCF_MTERM_CLR 0xefffffff
|
|
#define MPHI_HSINDCF_MTERM_MSB 28
|
|
#define MPHI_HSINDCF_MTERM_LSB 28
|
|
#define MPHI_HSINDCF_MTERM_RESET 0x0
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#define MPHI_HSINDCF_HANDLE_BITS 27:20
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#define MPHI_HSINDCF_HANDLE_SET 0x0ff00000
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#define MPHI_HSINDCF_HANDLE_CLR 0xf00fffff
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#define MPHI_HSINDCF_HANDLE_MSB 27
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#define MPHI_HSINDCF_HANDLE_LSB 20
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#define MPHI_HSINDCF_HANDLE_RESET 0x0
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#define MPHI_HSINDCF_LENGTH_BITS 19:0
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#define MPHI_HSINDCF_LENGTH_SET 0x000fffff
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#define MPHI_HSINDCF_LENGTH_CLR 0xfff00000
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#define MPHI_HSINDCF_LENGTH_MSB 19
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#define MPHI_HSINDCF_LENGTH_LSB 0
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#define MPHI_HSINDCF_LENGTH_RESET 0x0
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#define MPHI_HSINDS HW_REGISTER_RW( 0x7e006060 )
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#define MPHI_HSINDS_MASK 0xdfffffff
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#define MPHI_HSINDS_WIDTH 32
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#define MPHI_HSINDS_DISCARD_BITS 31:31
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#define MPHI_HSINDS_DISCARD_SET 0x80000000
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#define MPHI_HSINDS_DISCARD_CLR 0x7fffffff
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#define MPHI_HSINDS_DISCARD_MSB 31
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#define MPHI_HSINDS_DISCARD_LSB 31
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#define MPHI_HSINDS_DISCARD_RESET 0x0
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#define MPHI_HSINDS_VALID_BITS 30:30
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#define MPHI_HSINDS_VALID_SET 0x40000000
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#define MPHI_HSINDS_VALID_CLR 0xbfffffff
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#define MPHI_HSINDS_VALID_MSB 30
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#define MPHI_HSINDS_VALID_LSB 30
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#define MPHI_HSINDS_VALID_RESET 0x0
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#define MPHI_HSINDS_HANDLE_BITS 28:21
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#define MPHI_HSINDS_HANDLE_SET 0x1fe00000
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#define MPHI_HSINDS_HANDLE_CLR 0xe01fffff
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#define MPHI_HSINDS_HANDLE_MSB 28
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#define MPHI_HSINDS_HANDLE_LSB 21
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#define MPHI_HSINDS_HANDLE_RESET 0x0
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#define MPHI_HSINDS_WORDS_BITS 20:0
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#define MPHI_HSINDS_WORDS_SET 0x001fffff
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#define MPHI_HSINDS_WORDS_CLR 0xffe00000
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#define MPHI_HSINDS_WORDS_MSB 20
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#define MPHI_HSINDS_WORDS_LSB 0
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#define MPHI_HSINDS_WORDS_RESET 0x0
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#define MPHI_HSINDDA HW_REGISTER_RW( 0x7e006064 )
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#define MPHI_HSINDDA_MASK 0xffffffff
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#define MPHI_HSINDDA_WIDTH 32
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#define MPHI_HSINDDA_START_BITS 31:0
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#define MPHI_HSINDDA_START_SET 0xffffffff
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#define MPHI_HSINDDA_START_CLR 0x00000000
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#define MPHI_HSINDDA_START_MSB 31
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#define MPHI_HSINDDA_START_LSB 0
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#define MPHI_HSINDDA_START_RESET 0x0
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#define MPHI_HSINDDB HW_REGISTER_RW( 0x7e006068 )
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#define MPHI_HSINDDB_MASK 0x2fffffff
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#define MPHI_HSINDDB_WIDTH 30
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#define MPHI_HSINDDB_TENDINT_BITS 29:29
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#define MPHI_HSINDDB_TENDINT_SET 0x20000000
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#define MPHI_HSINDDB_TENDINT_CLR 0xdfffffff
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#define MPHI_HSINDDB_TENDINT_MSB 29
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#define MPHI_HSINDDB_TENDINT_LSB 29
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#define MPHI_HSINDDB_TENDINT_RESET 0x0
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#define MPHI_HSINDDB_HANDLE_BITS 27:20
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#define MPHI_HSINDDB_HANDLE_SET 0x0ff00000
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#define MPHI_HSINDDB_HANDLE_CLR 0xf00fffff
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#define MPHI_HSINDDB_HANDLE_MSB 27
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#define MPHI_HSINDDB_HANDLE_LSB 20
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#define MPHI_HSINDDB_HANDLE_RESET 0x0
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#define MPHI_HSINDDB_LENGTH_BITS 19:0
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#define MPHI_HSINDDB_LENGTH_SET 0x000fffff
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#define MPHI_HSINDDB_LENGTH_CLR 0xfff00000
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#define MPHI_HSINDDB_LENGTH_MSB 19
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#define MPHI_HSINDDB_LENGTH_LSB 0
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#define MPHI_HSINDDB_LENGTH_RESET 0x0
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#define MPHI_HSINDFS HW_REGISTER_RW( 0x7e00606c )
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#define MPHI_HSINDFS_MASK 0xffff0001
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#define MPHI_HSINDFS_WIDTH 32
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#define MPHI_HSINDFS_CFIFOLVL_BITS 31:16
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#define MPHI_HSINDFS_CFIFOLVL_SET 0xffff0000
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#define MPHI_HSINDFS_CFIFOLVL_CLR 0x0000ffff
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#define MPHI_HSINDFS_CFIFOLVL_MSB 31
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#define MPHI_HSINDFS_CFIFOLVL_LSB 16
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#define MPHI_HSINDFS_CFIFOLVL_RESET 0x0
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#define MPHI_HSINDFS_DFIFOLVL_BITS 0:0
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#define MPHI_HSINDFS_DFIFOLVL_SET 0x00000001
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#define MPHI_HSINDFS_DFIFOLVL_CLR 0xfffffffe
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#define MPHI_HSINDFS_DFIFOLVL_MSB 0
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#define MPHI_HSINDFS_DFIFOLVL_LSB 0
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#define MPHI_HSINDFS_DFIFOLVL_RESET 0x0
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