368 lines
26 KiB
C
Executable File
368 lines
26 KiB
C
Executable File
// This file was generated by the create_regs script
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#define PCM_BASE 0x7e203000
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#define PCM_CS_A HW_REGISTER_RW( 0x7e203000 )
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#define PCM_CS_A_MASK 0x03ffe3ff
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#define PCM_CS_A_WIDTH 26
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#define PCM_CS_A_RESET 0000000000
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#define PCM_CS_A_STBY_BITS 25:25
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#define PCM_CS_A_STBY_SET 0x02000000
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#define PCM_CS_A_STBY_CLR 0xfdffffff
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#define PCM_CS_A_STBY_MSB 25
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#define PCM_CS_A_STBY_LSB 25
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#define PCM_CS_A_SYNC_BITS 24:24
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#define PCM_CS_A_SYNC_SET 0x01000000
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#define PCM_CS_A_SYNC_CLR 0xfeffffff
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#define PCM_CS_A_SYNC_MSB 24
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#define PCM_CS_A_SYNC_LSB 24
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#define PCM_CS_A_RXSEX_BITS 23:23
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#define PCM_CS_A_RXSEX_SET 0x00800000
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#define PCM_CS_A_RXSEX_CLR 0xff7fffff
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#define PCM_CS_A_RXSEX_MSB 23
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#define PCM_CS_A_RXSEX_LSB 23
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#define PCM_CS_A_RXF_BITS 22:22
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#define PCM_CS_A_RXF_SET 0x00400000
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#define PCM_CS_A_RXF_CLR 0xffbfffff
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#define PCM_CS_A_RXF_MSB 22
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#define PCM_CS_A_RXF_LSB 22
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#define PCM_CS_A_TXE_BITS 21:21
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#define PCM_CS_A_TXE_SET 0x00200000
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#define PCM_CS_A_TXE_CLR 0xffdfffff
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#define PCM_CS_A_TXE_MSB 21
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#define PCM_CS_A_TXE_LSB 21
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#define PCM_CS_A_RXD_BITS 20:20
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#define PCM_CS_A_RXD_SET 0x00100000
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#define PCM_CS_A_RXD_CLR 0xffefffff
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#define PCM_CS_A_RXD_MSB 20
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#define PCM_CS_A_RXD_LSB 20
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#define PCM_CS_A_TXD_BITS 19:19
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#define PCM_CS_A_TXD_SET 0x00080000
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#define PCM_CS_A_TXD_CLR 0xfff7ffff
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#define PCM_CS_A_TXD_MSB 19
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#define PCM_CS_A_TXD_LSB 19
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#define PCM_CS_A_RXR_BITS 18:18
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#define PCM_CS_A_RXR_SET 0x00040000
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#define PCM_CS_A_RXR_CLR 0xfffbffff
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#define PCM_CS_A_RXR_MSB 18
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#define PCM_CS_A_RXR_LSB 18
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#define PCM_CS_A_TXW_BITS 17:17
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#define PCM_CS_A_TXW_SET 0x00020000
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#define PCM_CS_A_TXW_CLR 0xfffdffff
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#define PCM_CS_A_TXW_MSB 17
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#define PCM_CS_A_TXW_LSB 17
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#define PCM_CS_A_RXERR_BITS 16:16
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#define PCM_CS_A_RXERR_SET 0x00010000
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#define PCM_CS_A_RXERR_CLR 0xfffeffff
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#define PCM_CS_A_RXERR_MSB 16
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#define PCM_CS_A_RXERR_LSB 16
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#define PCM_CS_A_TXERR_BITS 15:15
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#define PCM_CS_A_TXERR_SET 0x00008000
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#define PCM_CS_A_TXERR_CLR 0xffff7fff
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#define PCM_CS_A_TXERR_MSB 15
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#define PCM_CS_A_TXERR_LSB 15
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#define PCM_CS_A_RXSYNC_BITS 14:14
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#define PCM_CS_A_RXSYNC_SET 0x00004000
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#define PCM_CS_A_RXSYNC_CLR 0xffffbfff
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#define PCM_CS_A_RXSYNC_MSB 14
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#define PCM_CS_A_RXSYNC_LSB 14
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#define PCM_CS_A_TXSYNC_BITS 13:13
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#define PCM_CS_A_TXSYNC_SET 0x00002000
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#define PCM_CS_A_TXSYNC_CLR 0xffffdfff
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#define PCM_CS_A_TXSYNC_MSB 13
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#define PCM_CS_A_TXSYNC_LSB 13
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#define PCM_CS_A_DMAEN_BITS 9:9
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#define PCM_CS_A_DMAEN_SET 0x00000200
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#define PCM_CS_A_DMAEN_CLR 0xfffffdff
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#define PCM_CS_A_DMAEN_MSB 9
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#define PCM_CS_A_DMAEN_LSB 9
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#define PCM_CS_A_RXTHR_BITS 8:7
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#define PCM_CS_A_RXTHR_SET 0x00000180
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#define PCM_CS_A_RXTHR_CLR 0xfffffe7f
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#define PCM_CS_A_RXTHR_MSB 8
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#define PCM_CS_A_RXTHR_LSB 7
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#define PCM_CS_A_TXTHR_BITS 6:5
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#define PCM_CS_A_TXTHR_SET 0x00000060
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#define PCM_CS_A_TXTHR_CLR 0xffffff9f
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#define PCM_CS_A_TXTHR_MSB 6
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#define PCM_CS_A_TXTHR_LSB 5
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#define PCM_CS_A_RXCLR_BITS 4:4
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#define PCM_CS_A_RXCLR_SET 0x00000010
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#define PCM_CS_A_RXCLR_CLR 0xffffffef
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#define PCM_CS_A_RXCLR_MSB 4
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#define PCM_CS_A_RXCLR_LSB 4
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#define PCM_CS_A_TXCLR_BITS 3:3
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#define PCM_CS_A_TXCLR_SET 0x00000008
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#define PCM_CS_A_TXCLR_CLR 0xfffffff7
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#define PCM_CS_A_TXCLR_MSB 3
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#define PCM_CS_A_TXCLR_LSB 3
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#define PCM_CS_A_TXON_BITS 2:2
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#define PCM_CS_A_TXON_SET 0x00000004
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#define PCM_CS_A_TXON_CLR 0xfffffffb
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#define PCM_CS_A_TXON_MSB 2
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#define PCM_CS_A_TXON_LSB 2
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#define PCM_CS_A_RXON_BITS 1:1
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#define PCM_CS_A_RXON_SET 0x00000002
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#define PCM_CS_A_RXON_CLR 0xfffffffd
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#define PCM_CS_A_RXON_MSB 1
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#define PCM_CS_A_RXON_LSB 1
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#define PCM_CS_A_EN_BITS 0:0
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#define PCM_CS_A_EN_SET 0x00000001
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#define PCM_CS_A_EN_CLR 0xfffffffe
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#define PCM_CS_A_EN_MSB 0
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#define PCM_CS_A_EN_LSB 0
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#define PCM_FIFO_A HW_REGISTER_RW( 0x7e203004 )
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#define PCM_FIFO_A_MASK 0xffffffff
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#define PCM_FIFO_A_WIDTH 32
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#define PCM_MODE_A HW_REGISTER_RW( 0x7e203008 )
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#define PCM_MODE_A_MASK 0x1fffffff
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#define PCM_MODE_A_WIDTH 29
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#define PCM_MODE_A_RESET 0000000000
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#define PCM_MODE_A_CLK_DIS_BITS 28:28
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#define PCM_MODE_A_CLK_DIS_SET 0x10000000
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#define PCM_MODE_A_CLK_DIS_CLR 0xefffffff
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#define PCM_MODE_A_CLK_DIS_MSB 28
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#define PCM_MODE_A_CLK_DIS_LSB 28
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#define PCM_MODE_A_PDMN_BITS 27:27
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#define PCM_MODE_A_PDMN_SET 0x08000000
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#define PCM_MODE_A_PDMN_CLR 0xf7ffffff
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#define PCM_MODE_A_PDMN_MSB 27
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#define PCM_MODE_A_PDMN_LSB 27
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#define PCM_MODE_A_PDME_BITS 26:26
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#define PCM_MODE_A_PDME_SET 0x04000000
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#define PCM_MODE_A_PDME_CLR 0xfbffffff
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#define PCM_MODE_A_PDME_MSB 26
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#define PCM_MODE_A_PDME_LSB 26
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#define PCM_MODE_A_FRXP_BITS 25:25
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#define PCM_MODE_A_FRXP_SET 0x02000000
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#define PCM_MODE_A_FRXP_CLR 0xfdffffff
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#define PCM_MODE_A_FRXP_MSB 25
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#define PCM_MODE_A_FRXP_LSB 25
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#define PCM_MODE_A_FTXP_BITS 24:24
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#define PCM_MODE_A_FTXP_SET 0x01000000
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#define PCM_MODE_A_FTXP_CLR 0xfeffffff
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#define PCM_MODE_A_FTXP_MSB 24
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#define PCM_MODE_A_FTXP_LSB 24
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#define PCM_MODE_A_CLKM_BITS 23:23
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#define PCM_MODE_A_CLKM_SET 0x00800000
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#define PCM_MODE_A_CLKM_CLR 0xff7fffff
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#define PCM_MODE_A_CLKM_MSB 23
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#define PCM_MODE_A_CLKM_LSB 23
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#define PCM_MODE_A_CLKI_BITS 22:22
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#define PCM_MODE_A_CLKI_SET 0x00400000
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#define PCM_MODE_A_CLKI_CLR 0xffbfffff
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#define PCM_MODE_A_CLKI_MSB 22
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#define PCM_MODE_A_CLKI_LSB 22
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#define PCM_MODE_A_FSM_BITS 21:21
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#define PCM_MODE_A_FSM_SET 0x00200000
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#define PCM_MODE_A_FSM_CLR 0xffdfffff
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#define PCM_MODE_A_FSM_MSB 21
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#define PCM_MODE_A_FSM_LSB 21
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#define PCM_MODE_A_FSI_BITS 20:20
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#define PCM_MODE_A_FSI_SET 0x00100000
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#define PCM_MODE_A_FSI_CLR 0xffefffff
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#define PCM_MODE_A_FSI_MSB 20
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#define PCM_MODE_A_FSI_LSB 20
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#define PCM_MODE_A_FLEN_BITS 19:10
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#define PCM_MODE_A_FLEN_SET 0x000ffc00
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#define PCM_MODE_A_FLEN_CLR 0xfff003ff
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#define PCM_MODE_A_FLEN_MSB 19
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#define PCM_MODE_A_FLEN_LSB 10
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#define PCM_MODE_A_FSLEN_BITS 9:0
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#define PCM_MODE_A_FSLEN_SET 0x000003ff
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#define PCM_MODE_A_FSLEN_CLR 0xfffffc00
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#define PCM_MODE_A_FSLEN_MSB 9
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#define PCM_MODE_A_FSLEN_LSB 0
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#define PCM_RXC_A HW_REGISTER_RW( 0x7e20300c )
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#define PCM_RXC_A_MASK 0xffffffff
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#define PCM_RXC_A_WIDTH 32
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#define PCM_RXC_A_RESET 0000000000
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#define PCM_RXC_A_CH1WEX_BITS 31:31
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#define PCM_RXC_A_CH1WEX_SET 0x80000000
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#define PCM_RXC_A_CH1WEX_CLR 0x7fffffff
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#define PCM_RXC_A_CH1WEX_MSB 31
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#define PCM_RXC_A_CH1WEX_LSB 31
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#define PCM_RXC_A_CH1EN_BITS 30:30
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#define PCM_RXC_A_CH1EN_SET 0x40000000
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#define PCM_RXC_A_CH1EN_CLR 0xbfffffff
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#define PCM_RXC_A_CH1EN_MSB 30
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#define PCM_RXC_A_CH1EN_LSB 30
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#define PCM_RXC_A_CH1POS_BITS 29:20
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#define PCM_RXC_A_CH1POS_SET 0x3ff00000
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#define PCM_RXC_A_CH1POS_CLR 0xc00fffff
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#define PCM_RXC_A_CH1POS_MSB 29
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#define PCM_RXC_A_CH1POS_LSB 20
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#define PCM_RXC_A_CH1WID_BITS 19:16
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#define PCM_RXC_A_CH1WID_SET 0x000f0000
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#define PCM_RXC_A_CH1WID_CLR 0xfff0ffff
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#define PCM_RXC_A_CH1WID_MSB 19
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#define PCM_RXC_A_CH1WID_LSB 16
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#define PCM_RXC_A_CH2WEX_BITS 15:15
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#define PCM_RXC_A_CH2WEX_SET 0x00008000
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#define PCM_RXC_A_CH2WEX_CLR 0xffff7fff
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#define PCM_RXC_A_CH2WEX_MSB 15
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#define PCM_RXC_A_CH2WEX_LSB 15
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#define PCM_RXC_A_CH2EN_BITS 14:14
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#define PCM_RXC_A_CH2EN_SET 0x00004000
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#define PCM_RXC_A_CH2EN_CLR 0xffffbfff
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#define PCM_RXC_A_CH2EN_MSB 14
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#define PCM_RXC_A_CH2EN_LSB 14
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#define PCM_RXC_A_CH2POS_BITS 13:4
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#define PCM_RXC_A_CH2POS_SET 0x00003ff0
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#define PCM_RXC_A_CH2POS_CLR 0xffffc00f
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#define PCM_RXC_A_CH2POS_MSB 13
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#define PCM_RXC_A_CH2POS_LSB 4
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#define PCM_RXC_A_CH2WID_BITS 3:0
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#define PCM_RXC_A_CH2WID_SET 0x0000000f
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#define PCM_RXC_A_CH2WID_CLR 0xfffffff0
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#define PCM_RXC_A_CH2WID_MSB 3
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#define PCM_RXC_A_CH2WID_LSB 0
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#define PCM_TXC_A HW_REGISTER_RW( 0x7e203010 )
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#define PCM_TXC_A_MASK 0xffffffff
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#define PCM_TXC_A_WIDTH 32
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#define PCM_TXC_A_RESET 0000000000
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#define PCM_TXC_A_CH1WEX_BITS 31:31
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#define PCM_TXC_A_CH1WEX_SET 0x80000000
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#define PCM_TXC_A_CH1WEX_CLR 0x7fffffff
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#define PCM_TXC_A_CH1WEX_MSB 31
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#define PCM_TXC_A_CH1WEX_LSB 31
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#define PCM_TXC_A_CH1EN_BITS 30:30
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#define PCM_TXC_A_CH1EN_SET 0x40000000
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#define PCM_TXC_A_CH1EN_CLR 0xbfffffff
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#define PCM_TXC_A_CH1EN_MSB 30
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#define PCM_TXC_A_CH1EN_LSB 30
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#define PCM_TXC_A_CH1POS_BITS 29:20
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#define PCM_TXC_A_CH1POS_SET 0x3ff00000
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#define PCM_TXC_A_CH1POS_CLR 0xc00fffff
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#define PCM_TXC_A_CH1POS_MSB 29
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#define PCM_TXC_A_CH1POS_LSB 20
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#define PCM_TXC_A_CH1WID_BITS 19:16
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#define PCM_TXC_A_CH1WID_SET 0x000f0000
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#define PCM_TXC_A_CH1WID_CLR 0xfff0ffff
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#define PCM_TXC_A_CH1WID_MSB 19
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#define PCM_TXC_A_CH1WID_LSB 16
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#define PCM_TXC_A_CH2WEX_BITS 15:15
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#define PCM_TXC_A_CH2WEX_SET 0x00008000
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#define PCM_TXC_A_CH2WEX_CLR 0xffff7fff
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#define PCM_TXC_A_CH2WEX_MSB 15
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#define PCM_TXC_A_CH2WEX_LSB 15
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#define PCM_TXC_A_CH2EN_BITS 14:14
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#define PCM_TXC_A_CH2EN_SET 0x00004000
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#define PCM_TXC_A_CH2EN_CLR 0xffffbfff
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#define PCM_TXC_A_CH2EN_MSB 14
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#define PCM_TXC_A_CH2EN_LSB 14
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#define PCM_TXC_A_CH2POS_BITS 13:4
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#define PCM_TXC_A_CH2POS_SET 0x00003ff0
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#define PCM_TXC_A_CH2POS_CLR 0xffffc00f
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#define PCM_TXC_A_CH2POS_MSB 13
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#define PCM_TXC_A_CH2POS_LSB 4
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#define PCM_TXC_A_CH2WID_BITS 3:0
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#define PCM_TXC_A_CH2WID_SET 0x0000000f
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#define PCM_TXC_A_CH2WID_CLR 0xfffffff0
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#define PCM_TXC_A_CH2WID_MSB 3
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#define PCM_TXC_A_CH2WID_LSB 0
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#define PCM_DREQ_A HW_REGISTER_RW( 0x7e203014 )
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#define PCM_DREQ_A_MASK 0x7f7f7f7f
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#define PCM_DREQ_A_WIDTH 31
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#define PCM_DREQ_A_RESET 0x10303020
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#define PCM_DREQ_A_TX_PANIC_BITS 30:24
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#define PCM_DREQ_A_TX_PANIC_SET 0x7f000000
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#define PCM_DREQ_A_TX_PANIC_CLR 0x80ffffff
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#define PCM_DREQ_A_TX_PANIC_MSB 30
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#define PCM_DREQ_A_TX_PANIC_LSB 24
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#define PCM_DREQ_A_RX_PANIC_BITS 22:16
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#define PCM_DREQ_A_RX_PANIC_SET 0x007f0000
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#define PCM_DREQ_A_RX_PANIC_CLR 0xff80ffff
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#define PCM_DREQ_A_RX_PANIC_MSB 22
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#define PCM_DREQ_A_RX_PANIC_LSB 16
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#define PCM_DREQ_A_TX_BITS 14:8
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#define PCM_DREQ_A_TX_SET 0x00007f00
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#define PCM_DREQ_A_TX_CLR 0xffff80ff
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#define PCM_DREQ_A_TX_MSB 14
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#define PCM_DREQ_A_TX_LSB 8
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#define PCM_DREQ_A_RX_BITS 6:0
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#define PCM_DREQ_A_RX_SET 0x0000007f
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#define PCM_DREQ_A_RX_CLR 0xffffff80
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#define PCM_DREQ_A_RX_MSB 6
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#define PCM_DREQ_A_RX_LSB 0
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#define PCM_INTEN_A HW_REGISTER_RW( 0x7e203018 )
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#define PCM_INTEN_A_MASK 0x0000000f
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#define PCM_INTEN_A_WIDTH 4
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#define PCM_INTEN_A_RESET 0000000000
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#define PCM_INTEN_A_RXERR_BITS 3:3
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#define PCM_INTEN_A_RXERR_SET 0x00000008
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#define PCM_INTEN_A_RXERR_CLR 0xfffffff7
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#define PCM_INTEN_A_RXERR_MSB 3
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#define PCM_INTEN_A_RXERR_LSB 3
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#define PCM_INTEN_A_TXERR_BITS 2:2
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#define PCM_INTEN_A_TXERR_SET 0x00000004
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#define PCM_INTEN_A_TXERR_CLR 0xfffffffb
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#define PCM_INTEN_A_TXERR_MSB 2
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#define PCM_INTEN_A_TXERR_LSB 2
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#define PCM_INTEN_A_RXR_BITS 1:1
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#define PCM_INTEN_A_RXR_SET 0x00000002
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#define PCM_INTEN_A_RXR_CLR 0xfffffffd
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#define PCM_INTEN_A_RXR_MSB 1
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#define PCM_INTEN_A_RXR_LSB 1
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#define PCM_INTEN_A_TXW_BITS 0:0
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#define PCM_INTEN_A_TXW_SET 0x00000001
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#define PCM_INTEN_A_TXW_CLR 0xfffffffe
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#define PCM_INTEN_A_TXW_MSB 0
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#define PCM_INTEN_A_TXW_LSB 0
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#define PCM_INTSTC_A HW_REGISTER_RW( 0x7e20301c )
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#define PCM_INTSTC_A_MASK 0x0000000f
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#define PCM_INTSTC_A_WIDTH 4
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#define PCM_INTSTC_A_RESET 0000000000
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#define PCM_INTSTC_A_RXERR_BITS 3:3
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#define PCM_INTSTC_A_RXERR_SET 0x00000008
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#define PCM_INTSTC_A_RXERR_CLR 0xfffffff7
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#define PCM_INTSTC_A_RXERR_MSB 3
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#define PCM_INTSTC_A_RXERR_LSB 3
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#define PCM_INTSTC_A_TXERR_BITS 2:2
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#define PCM_INTSTC_A_TXERR_SET 0x00000004
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#define PCM_INTSTC_A_TXERR_CLR 0xfffffffb
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#define PCM_INTSTC_A_TXERR_MSB 2
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#define PCM_INTSTC_A_TXERR_LSB 2
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#define PCM_INTSTC_A_RXR_BITS 1:1
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#define PCM_INTSTC_A_RXR_SET 0x00000002
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#define PCM_INTSTC_A_RXR_CLR 0xfffffffd
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#define PCM_INTSTC_A_RXR_MSB 1
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#define PCM_INTSTC_A_RXR_LSB 1
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#define PCM_INTSTC_A_TXW_BITS 0:0
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#define PCM_INTSTC_A_TXW_SET 0x00000001
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#define PCM_INTSTC_A_TXW_CLR 0xfffffffe
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#define PCM_INTSTC_A_TXW_MSB 0
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#define PCM_INTSTC_A_TXW_LSB 0
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#define PCM_GRAY HW_REGISTER_RW( 0x7e203020 )
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#define PCM_GRAY_MASK 0x003ffff7
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#define PCM_GRAY_WIDTH 22
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#define PCM_GRAY_RESET 0000000000
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#define PCM_GRAY_RXFIFOLEVEL_BITS 21:16
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#define PCM_GRAY_RXFIFOLEVEL_SET 0x003f0000
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#define PCM_GRAY_RXFIFOLEVEL_CLR 0xffc0ffff
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#define PCM_GRAY_RXFIFOLEVEL_MSB 21
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#define PCM_GRAY_RXFIFOLEVEL_LSB 16
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#define PCM_GRAY_FLUSHED_BITS 15:10
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#define PCM_GRAY_FLUSHED_SET 0x0000fc00
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#define PCM_GRAY_FLUSHED_CLR 0xffff03ff
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#define PCM_GRAY_FLUSHED_MSB 15
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#define PCM_GRAY_FLUSHED_LSB 10
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#define PCM_GRAY_RXLEVEL_BITS 9:4
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#define PCM_GRAY_RXLEVEL_SET 0x000003f0
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#define PCM_GRAY_RXLEVEL_CLR 0xfffffc0f
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#define PCM_GRAY_RXLEVEL_MSB 9
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#define PCM_GRAY_RXLEVEL_LSB 4
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#define PCM_GRAY_FLUSH_BITS 2:2
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#define PCM_GRAY_FLUSH_SET 0x00000004
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#define PCM_GRAY_FLUSH_CLR 0xfffffffb
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#define PCM_GRAY_FLUSH_MSB 2
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#define PCM_GRAY_FLUSH_LSB 2
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#define PCM_GRAY_CLR_BITS 1:1
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#define PCM_GRAY_CLR_SET 0x00000002
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#define PCM_GRAY_CLR_CLR 0xfffffffd
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#define PCM_GRAY_CLR_MSB 1
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#define PCM_GRAY_CLR_LSB 1
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#define PCM_GRAY_EN_BITS 0:0
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#define PCM_GRAY_EN_SET 0x00000001
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#define PCM_GRAY_EN_CLR 0xfffffffe
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#define PCM_GRAY_EN_MSB 0
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#define PCM_GRAY_EN_LSB 0
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