260 lines
18 KiB
C
Executable File
260 lines
18 KiB
C
Executable File
// This file was generated by the create_regs script
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#define SH_BASE 0x7e202000
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#define SH_CMD HW_REGISTER_RW( 0x7e202000 )
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#define SH_CMD_MASK 0x0000cfff
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#define SH_CMD_WIDTH 16
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#define SH_CMD_RESET 0000000000
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#define SH_CMD_NEW_FLAG_BITS 15:15
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#define SH_CMD_NEW_FLAG_SET 0x00008000
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#define SH_CMD_NEW_FLAG_CLR 0xffff7fff
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#define SH_CMD_NEW_FLAG_MSB 15
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#define SH_CMD_NEW_FLAG_LSB 15
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#define SH_CMD_FAIL_FLAG_BITS 14:14
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#define SH_CMD_FAIL_FLAG_SET 0x00004000
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#define SH_CMD_FAIL_FLAG_CLR 0xffffbfff
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#define SH_CMD_FAIL_FLAG_MSB 14
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#define SH_CMD_FAIL_FLAG_LSB 14
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#define SH_CMD_BUSY_CMD_BITS 11:11
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#define SH_CMD_BUSY_CMD_SET 0x00000800
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#define SH_CMD_BUSY_CMD_CLR 0xfffff7ff
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#define SH_CMD_BUSY_CMD_MSB 11
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#define SH_CMD_BUSY_CMD_LSB 11
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#define SH_CMD_NO_RESPONSE_BITS 10:10
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#define SH_CMD_NO_RESPONSE_SET 0x00000400
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#define SH_CMD_NO_RESPONSE_CLR 0xfffffbff
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#define SH_CMD_NO_RESPONSE_MSB 10
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#define SH_CMD_NO_RESPONSE_LSB 10
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#define SH_CMD_LONG_RESPONSE_BITS 9:9
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#define SH_CMD_LONG_RESPONSE_SET 0x00000200
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#define SH_CMD_LONG_RESPONSE_CLR 0xfffffdff
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#define SH_CMD_LONG_RESPONSE_MSB 9
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#define SH_CMD_LONG_RESPONSE_LSB 9
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#define SH_CMD_WRITE_CMD_BITS 8:7
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#define SH_CMD_WRITE_CMD_SET 0x00000180
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#define SH_CMD_WRITE_CMD_CLR 0xfffffe7f
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#define SH_CMD_WRITE_CMD_MSB 8
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#define SH_CMD_WRITE_CMD_LSB 7
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#define SH_CMD_READ_CMD_BITS 6:6
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#define SH_CMD_READ_CMD_SET 0x00000040
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#define SH_CMD_READ_CMD_CLR 0xffffffbf
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#define SH_CMD_READ_CMD_MSB 6
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#define SH_CMD_READ_CMD_LSB 6
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#define SH_CMD_COMMAND_BITS 5:0
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#define SH_CMD_COMMAND_SET 0x0000003f
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#define SH_CMD_COMMAND_CLR 0xffffffc0
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#define SH_CMD_COMMAND_MSB 5
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#define SH_CMD_COMMAND_LSB 0
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#define SH_ARG HW_REGISTER_RW( 0x7e202004 )
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#define SH_ARG_MASK 0xffffffff
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#define SH_ARG_WIDTH 32
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#define SH_ARG_RESET 0000000000
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#define SH_ARG_ARGUMENT_BITS 31:0
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#define SH_ARG_ARGUMENT_SET 0xffffffff
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#define SH_ARG_ARGUMENT_CLR 0x00000000
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#define SH_ARG_ARGUMENT_MSB 31
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#define SH_ARG_ARGUMENT_LSB 0
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#define SH_TOUT HW_REGISTER_RW( 0x7e202008 )
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#define SH_TOUT_MASK 0xffffffff
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#define SH_TOUT_WIDTH 32
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#define SH_TOUT_RESET 0x00a00000
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#define SH_TOUT_TIME_OUT_BITS 31:0
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#define SH_TOUT_TIME_OUT_SET 0xffffffff
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#define SH_TOUT_TIME_OUT_CLR 0x00000000
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#define SH_TOUT_TIME_OUT_MSB 31
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#define SH_TOUT_TIME_OUT_LSB 0
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#define SH_CDIV HW_REGISTER_RW( 0x7e20200c )
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#define SH_CDIV_MASK 0x000007ff
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#define SH_CDIV_WIDTH 11
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#define SH_CDIV_RESET 0x000001fb
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#define SH_CDIV_CLOCKDIV_BITS 10:0
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#define SH_CDIV_CLOCKDIV_SET 0x000007ff
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#define SH_CDIV_CLOCKDIV_CLR 0xfffff800
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#define SH_CDIV_CLOCKDIV_MSB 10
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#define SH_CDIV_CLOCKDIV_LSB 0
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#define SH_RSP0 HW_REGISTER_RO( 0x7e202010 )
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#define SH_RSP0_MASK 0xffffffff
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#define SH_RSP0_WIDTH 32
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#define SH_RSP0_CARD_STATUS_BITS 31:0
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#define SH_RSP0_CARD_STATUS_SET 0xffffffff
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#define SH_RSP0_CARD_STATUS_CLR 0x00000000
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#define SH_RSP0_CARD_STATUS_MSB 31
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#define SH_RSP0_CARD_STATUS_LSB 0
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#define SH_RSP1 HW_REGISTER_RO( 0x7e202014 )
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#define SH_RSP1_MASK 0xffffffff
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#define SH_RSP1_WIDTH 32
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#define SH_RSP1_RESET 0000000000
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#define SH_RSP1_CID_CSD_BITS 31:0
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#define SH_RSP1_CID_CSD_SET 0xffffffff
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#define SH_RSP1_CID_CSD_CLR 0x00000000
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#define SH_RSP1_CID_CSD_MSB 31
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#define SH_RSP1_CID_CSD_LSB 0
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#define SH_RSP2 HW_REGISTER_RO( 0x7e202018 )
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#define SH_RSP2_MASK 0xffffffff
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#define SH_RSP2_WIDTH 32
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#define SH_RSP2_RESET 0000000000
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#define SH_RSP2_CID_CSD_BITS 31:0
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#define SH_RSP2_CID_CSD_SET 0xffffffff
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#define SH_RSP2_CID_CSD_CLR 0x00000000
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#define SH_RSP2_CID_CSD_MSB 31
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#define SH_RSP2_CID_CSD_LSB 0
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#define SH_RSP3 HW_REGISTER_RO( 0x7e20201c )
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#define SH_RSP3_MASK 0xffffffff
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#define SH_RSP3_WIDTH 32
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#define SH_RSP3_RESET 0000000000
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#define SH_RSP3_CID_CSD_BITS 31:0
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#define SH_RSP3_CID_CSD_SET 0xffffffff
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#define SH_RSP3_CID_CSD_CLR 0x00000000
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#define SH_RSP3_CID_CSD_MSB 31
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#define SH_RSP3_CID_CSD_LSB 0
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#define SH_HSTS HW_REGISTER_RW( 0x7e202020 )
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#define SH_HSTS_MASK 0x000007f9
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#define SH_HSTS_WIDTH 11
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#define SH_HSTS_RESET 0000000000
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#define SH_HSTS_BUSY_IRPT_BITS 10:10
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#define SH_HSTS_BUSY_IRPT_SET 0x00000400
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#define SH_HSTS_BUSY_IRPT_CLR 0xfffffbff
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#define SH_HSTS_BUSY_IRPT_MSB 10
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#define SH_HSTS_BUSY_IRPT_LSB 10
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#define SH_HSTS_BLOCK_IRPT_BITS 9:9
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#define SH_HSTS_BLOCK_IRPT_SET 0x00000200
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#define SH_HSTS_BLOCK_IRPT_CLR 0xfffffdff
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#define SH_HSTS_BLOCK_IRPT_MSB 9
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#define SH_HSTS_BLOCK_IRPT_LSB 9
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#define SH_HSTS_SDIO_IRPT_BITS 8:8
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#define SH_HSTS_SDIO_IRPT_SET 0x00000100
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#define SH_HSTS_SDIO_IRPT_CLR 0xfffffeff
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#define SH_HSTS_SDIO_IRPT_MSB 8
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#define SH_HSTS_SDIO_IRPT_LSB 8
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#define SH_HSTS_REW_TIME_OUT_BITS 7:7
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#define SH_HSTS_REW_TIME_OUT_SET 0x00000080
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#define SH_HSTS_REW_TIME_OUT_CLR 0xffffff7f
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#define SH_HSTS_REW_TIME_OUT_MSB 7
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#define SH_HSTS_REW_TIME_OUT_LSB 7
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#define SH_HSTS_CMD_TIME_OUT_BITS 6:6
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#define SH_HSTS_CMD_TIME_OUT_SET 0x00000040
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#define SH_HSTS_CMD_TIME_OUT_CLR 0xffffffbf
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#define SH_HSTS_CMD_TIME_OUT_MSB 6
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#define SH_HSTS_CMD_TIME_OUT_LSB 6
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#define SH_HSTS_CRC16_ERROR_BITS 5:5
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#define SH_HSTS_CRC16_ERROR_SET 0x00000020
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#define SH_HSTS_CRC16_ERROR_CLR 0xffffffdf
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#define SH_HSTS_CRC16_ERROR_MSB 5
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#define SH_HSTS_CRC16_ERROR_LSB 5
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#define SH_HSTS_CRC7_ERROR_BITS 4:4
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#define SH_HSTS_CRC7_ERROR_SET 0x00000010
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#define SH_HSTS_CRC7_ERROR_CLR 0xffffffef
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#define SH_HSTS_CRC7_ERROR_MSB 4
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#define SH_HSTS_CRC7_ERROR_LSB 4
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#define SH_HSTS_FIFO_ERROR_BITS 3:3
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#define SH_HSTS_FIFO_ERROR_SET 0x00000008
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#define SH_HSTS_FIFO_ERROR_CLR 0xfffffff7
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#define SH_HSTS_FIFO_ERROR_MSB 3
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#define SH_HSTS_FIFO_ERROR_LSB 3
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#define SH_HSTS_DATA_FLAG_BITS 0:0
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#define SH_HSTS_DATA_FLAG_SET 0x00000001
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#define SH_HSTS_DATA_FLAG_CLR 0xfffffffe
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#define SH_HSTS_DATA_FLAG_MSB 0
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#define SH_HSTS_DATA_FLAG_LSB 0
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#define SH_VDD HW_REGISTER_RW( 0x7e202030 )
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#define SH_VDD_MASK 0x00000001
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#define SH_VDD_WIDTH 1
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#define SH_VDD_RESET 0000000000
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#define SH_VDD_POWER_ON_BITS 0:0
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#define SH_VDD_POWER_ON_SET 0x00000001
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#define SH_VDD_POWER_ON_CLR 0xfffffffe
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#define SH_VDD_POWER_ON_MSB 0
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#define SH_VDD_POWER_ON_LSB 0
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#define SH_EDM HW_REGISTER_RW( 0x7e202034 )
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#define SH_EDM_MASK 0x0007ffff
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#define SH_EDM_WIDTH 19
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#define SH_EDM_READ_THRESHOLD_BITS 18:14
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#define SH_EDM_READ_THRESHOLD_SET 0x0007c000
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#define SH_EDM_READ_THRESHOLD_CLR 0xfff83fff
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#define SH_EDM_READ_THRESHOLD_MSB 18
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#define SH_EDM_READ_THRESHOLD_LSB 14
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#define SH_EDM_WRITE_THRESHOLD_BITS 13:9
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#define SH_EDM_WRITE_THRESHOLD_SET 0x00003e00
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#define SH_EDM_WRITE_THRESHOLD_CLR 0xffffc1ff
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#define SH_EDM_WRITE_THRESHOLD_MSB 13
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#define SH_EDM_WRITE_THRESHOLD_LSB 9
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#define SH_EDM_FIFO_COUNT_BITS 8:4
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#define SH_EDM_FIFO_COUNT_SET 0x000001f0
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#define SH_EDM_FIFO_COUNT_CLR 0xfffffe0f
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#define SH_EDM_FIFO_COUNT_MSB 8
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#define SH_EDM_FIFO_COUNT_LSB 4
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#define SH_EDM_STATE_MACHINE_BITS 3:0
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#define SH_EDM_STATE_MACHINE_SET 0x0000000f
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#define SH_EDM_STATE_MACHINE_CLR 0xfffffff0
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#define SH_EDM_STATE_MACHINE_MSB 3
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#define SH_EDM_STATE_MACHINE_LSB 0
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#define SH_HCFG HW_REGISTER_RW( 0x7e202038 )
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#define SH_HCFG_MASK 0x0000073f
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#define SH_HCFG_WIDTH 11
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#define SH_HCFG_RESET 0000000000
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#define SH_HCFG_BUSY_IRPT_EN_BITS 10:10
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#define SH_HCFG_BUSY_IRPT_EN_SET 0x00000400
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#define SH_HCFG_BUSY_IRPT_EN_CLR 0xfffffbff
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#define SH_HCFG_BUSY_IRPT_EN_MSB 10
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#define SH_HCFG_BUSY_IRPT_EN_LSB 10
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#define SH_HCFG_BLOCK_IRPT_EN_BITS 8:8
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#define SH_HCFG_BLOCK_IRPT_EN_SET 0x00000100
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#define SH_HCFG_BLOCK_IRPT_EN_CLR 0xfffffeff
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#define SH_HCFG_BLOCK_IRPT_EN_MSB 8
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#define SH_HCFG_BLOCK_IRPT_EN_LSB 8
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#define SH_HCFG_SDIO_IRPT_EN_BITS 5:5
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#define SH_HCFG_SDIO_IRPT_EN_SET 0x00000020
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#define SH_HCFG_SDIO_IRPT_EN_CLR 0xffffffdf
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#define SH_HCFG_SDIO_IRPT_EN_MSB 5
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#define SH_HCFG_SDIO_IRPT_EN_LSB 5
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#define SH_HCFG_DATA_IRPT_EN_BITS 4:4
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#define SH_HCFG_DATA_IRPT_EN_SET 0x00000010
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#define SH_HCFG_DATA_IRPT_EN_CLR 0xffffffef
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#define SH_HCFG_DATA_IRPT_EN_MSB 4
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#define SH_HCFG_DATA_IRPT_EN_LSB 4
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#define SH_HCFG_SLOW_CARD_BITS 3:3
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#define SH_HCFG_SLOW_CARD_SET 0x00000008
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#define SH_HCFG_SLOW_CARD_CLR 0xfffffff7
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#define SH_HCFG_SLOW_CARD_MSB 3
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#define SH_HCFG_SLOW_CARD_LSB 3
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#define SH_HCFG_WIDE_EXT_BUS_BITS 2:2
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#define SH_HCFG_WIDE_EXT_BUS_SET 0x00000004
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#define SH_HCFG_WIDE_EXT_BUS_CLR 0xfffffffb
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#define SH_HCFG_WIDE_EXT_BUS_MSB 2
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#define SH_HCFG_WIDE_EXT_BUS_LSB 2
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#define SH_HCFG_WIDE_INT_BUS_BITS 1:1
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#define SH_HCFG_WIDE_INT_BUS_SET 0x00000002
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#define SH_HCFG_WIDE_INT_BUS_CLR 0xfffffffd
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#define SH_HCFG_WIDE_INT_BUS_MSB 1
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#define SH_HCFG_WIDE_INT_BUS_LSB 1
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#define SH_HCFG_REL_CMD_LINE_BITS 0:0
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#define SH_HCFG_REL_CMD_LINE_SET 0x00000001
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#define SH_HCFG_REL_CMD_LINE_CLR 0xfffffffe
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#define SH_HCFG_REL_CMD_LINE_MSB 0
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#define SH_HCFG_REL_CMD_LINE_LSB 0
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#define SH_HBCT HW_REGISTER_RW( 0x7e20203c )
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#define SH_HBCT_MASK 0xffffffff
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#define SH_HBCT_WIDTH 32
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#define SH_HBCT_RESET 0x00000400
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#define SH_HBCT_BYTECOUNT_BITS 31:0
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#define SH_HBCT_BYTECOUNT_SET 0xffffffff
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#define SH_HBCT_BYTECOUNT_CLR 0x00000000
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#define SH_HBCT_BYTECOUNT_MSB 31
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#define SH_HBCT_BYTECOUNT_LSB 0
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#define SH_DATA HW_REGISTER_RW( 0x7e202040 )
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#define SH_DATA_MASK 0xffffffff
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#define SH_DATA_WIDTH 32
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#define SH_DATA_DATA_BITS 31:0
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#define SH_DATA_DATA_SET 0xffffffff
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#define SH_DATA_DATA_CLR 0x00000000
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#define SH_DATA_DATA_MSB 31
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#define SH_DATA_DATA_LSB 0
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#define SH_HBLC HW_REGISTER_RW( 0x7e202050 )
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#define SH_HBLC_MASK 0x0000ffff
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#define SH_HBLC_WIDTH 16
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#define SH_HBLC_RESET 0000000000
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#define SH_HBLC_BLOCKCOUNT_BITS 8:0
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#define SH_HBLC_BLOCKCOUNT_SET 0x000001ff
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#define SH_HBLC_BLOCKCOUNT_CLR 0xfffffe00
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#define SH_HBLC_BLOCKCOUNT_MSB 8
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#define SH_HBLC_BLOCKCOUNT_LSB 0
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