228 lines
17 KiB
C
Executable File
228 lines
17 KiB
C
Executable File
// This file was generated by the create_regs script
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#define SLIM_BASE 0x7e210000
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#define SLIM_APB_ID 0x736c696d
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#define SLIM_CON HW_REGISTER_RW( 0x7e210000 )
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#define SLIM_CON_MASK 0xffffffff
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#define SLIM_CON_WIDTH 32
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#define SLIM_CON_RESET 0x000005c1
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#define SLIM_STAT HW_REGISTER_RW( 0x7e210004 )
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#define SLIM_STAT_MASK 0x03ffffff
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#define SLIM_STAT_WIDTH 26
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#define SLIM_STAT_RESET 0000000000
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#define SLIM_FS HW_REGISTER_RW( 0x7e210008 )
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#define SLIM_FS_MASK 0x00003fff
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#define SLIM_FS_WIDTH 14
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#define SLIM_FS_RESET 0000000000
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#define SLIM_CON2 HW_REGISTER_RW( 0x7e210008 )
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#define SLIM_CON2_MASK 0x00000001
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#define SLIM_CON2_WIDTH 1
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#define SLIM_CON2_RESET 0000000000
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#define SLIM_DMA_SMC_RX HW_REGISTER_RW( 0x7e210010 )
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#define SLIM_DMA_SMC_RX_MASK 0xffffffff
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#define SLIM_DMA_SMC_RX_WIDTH 32
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#define SLIM_DMA_SMC_RX_RESET 0000000000
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#define SLIM_DMA_SMC_TX HW_REGISTER_RW( 0x7e210014 )
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#define SLIM_DMA_SMC_TX_MASK 0xffffffff
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#define SLIM_DMA_SMC_TX_WIDTH 32
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#define SLIM_DMA_SMC_TX_RESET 0000000000
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#define SLIM_DMA_DC_RX HW_REGISTER_RW( 0x7e210018 )
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#define SLIM_DMA_DC_RX_MASK 0xffffffff
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#define SLIM_DMA_DC_RX_WIDTH 32
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#define SLIM_DMA_DC_RX_RESET 0000000000
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#define SLIM_DMA_DC_TX HW_REGISTER_RW( 0x7e21001c )
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#define SLIM_DMA_DC_TX_MASK 0xffffffff
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#define SLIM_DMA_DC_TX_WIDTH 32
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#define SLIM_DMA_DC_TX_RESET 0000000000
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#define SLIM_DMA_CON HW_REGISTER_RW( 0x7e210020 )
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#define SLIM_DMA_CON_MASK 0x0000000f
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#define SLIM_DMA_CON_WIDTH 4
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#define SLIM_DMA_CON_RESET 0000000000
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#define SLIM_DMA_STAT HW_REGISTER_RW( 0x7e210024 )
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#define SLIM_DMA_STAT_MASK 0x000000ff
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#define SLIM_DMA_STAT_WIDTH 8
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#define SLIM_DMA_STAT_RESET 0000000000
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#define SLIM_EA0 HW_REGISTER_RW( 0x7e210030 )
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#define SLIM_EA0_MASK 0xffff00ff
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#define SLIM_EA0_WIDTH 32
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#define SLIM_EA0_RESET 0000000000
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#define SLIM_EA1 HW_REGISTER_RW( 0x7e210034 )
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#define SLIM_EA1_MASK 0x8000ffff
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#define SLIM_EA1_WIDTH 32
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#define SLIM_EA1_RESET 0000000000
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#define SLIM_SMC_IN_CON HW_REGISTER_RW( 0x7e210100 )
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#define SLIM_SMC_IN_CON_MASK 0x00000f0f
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#define SLIM_SMC_IN_CON_WIDTH 12
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#define SLIM_SMC_IN_CON_RESET 0000000000
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#define SLIM_SMC_IN_STAT HW_REGISTER_RW( 0x7e210104 )
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#define SLIM_SMC_IN_STAT_MASK 0x0000000f
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#define SLIM_SMC_IN_STAT_WIDTH 4
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#define SLIM_SMC_IN_STAT_RESET 0000000000
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#define SLIM_SMC_OUT_CON HW_REGISTER_RW( 0x7e210120 )
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#define SLIM_SMC_OUT_CON_MASK 0x000000c8
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#define SLIM_SMC_OUT_CON_WIDTH 8
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#define SLIM_SMC_OUT_CON_RESET 0000000000
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#define SLIM_SMC_OUT_STAT HW_REGISTER_RW( 0x7e210124 )
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#define SLIM_SMC_OUT_STAT_MASK 0x0000000c
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#define SLIM_SMC_OUT_STAT_WIDTH 4
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#define SLIM_SMC_OUT_STAT_RESET 0000000000
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#define SLIM_DCC0_PA0 HW_REGISTER_RW( 0x7e210200 )
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#define SLIM_DCC0_PA0_MASK 0x00ffff1f
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#define SLIM_DCC0_PA0_WIDTH 24
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#define SLIM_DCC0_PA0_RESET 0000000000
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#define SLIM_DCC0_PA1 HW_REGISTER_RW( 0x7e210204 )
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#define SLIM_DCC0_PA1_MASK 0x00ffff3f
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#define SLIM_DCC0_PA1_WIDTH 24
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#define SLIM_DCC0_PA1_RESET 0000000000
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#define SLIM_DCC0_CON HW_REGISTER_RW( 0x7e210208 )
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#define SLIM_DCC0_CON_MASK 0xffff0073
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#define SLIM_DCC0_CON_WIDTH 32
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#define SLIM_DCC0_CON_RESET 0000000000
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#define SLIM_DCC0_STAT HW_REGISTER_RW( 0x7e21020c )
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#define SLIM_DCC0_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC0_STAT_WIDTH 32
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#define SLIM_DCC0_STAT_RESET 0000000000
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#define SLIM_DCC1_PA0 HW_REGISTER_RW( 0x7e210220 )
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#define SLIM_DCC1_PA0_MASK 0x00ffff1f
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#define SLIM_DCC1_PA0_WIDTH 24
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#define SLIM_DCC1_PA0_RESET 0000000000
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#define SLIM_DCC1_PA1 HW_REGISTER_RW( 0x7e210224 )
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#define SLIM_DCC1_PA1_MASK 0x00ffff3f
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#define SLIM_DCC1_PA1_WIDTH 24
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#define SLIM_DCC1_PA1_RESET 0000000000
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#define SLIM_DCC1_CON HW_REGISTER_RW( 0x7e210228 )
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#define SLIM_DCC1_CON_MASK 0xffff0073
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#define SLIM_DCC1_CON_WIDTH 32
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#define SLIM_DCC1_CON_RESET 0000000000
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#define SLIM_DCC1_STAT HW_REGISTER_RW( 0x7e21022c )
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#define SLIM_DCC1_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC1_STAT_WIDTH 32
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#define SLIM_DCC1_STAT_RESET 0000000000
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#define SLIM_DCC2_PA0 HW_REGISTER_RW( 0x7e210240 )
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#define SLIM_DCC2_PA0_MASK 0x00ffff1f
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#define SLIM_DCC2_PA0_WIDTH 24
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#define SLIM_DCC2_PA0_RESET 0000000000
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#define SLIM_DCC2_PA1 HW_REGISTER_RW( 0x7e210244 )
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#define SLIM_DCC2_PA1_MASK 0x00ffff3f
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#define SLIM_DCC2_PA1_WIDTH 24
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#define SLIM_DCC2_PA1_RESET 0000000000
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#define SLIM_DCC2_CON HW_REGISTER_RW( 0x7e210248 )
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#define SLIM_DCC2_CON_MASK 0xffff0073
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#define SLIM_DCC2_CON_WIDTH 32
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#define SLIM_DCC2_CON_RESET 0000000000
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#define SLIM_DCC2_STAT HW_REGISTER_RW( 0x7e21024c )
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#define SLIM_DCC2_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC2_STAT_WIDTH 32
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#define SLIM_DCC2_STAT_RESET 0000000000
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#define SLIM_DCC3_PA0 HW_REGISTER_RW( 0x7e210260 )
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#define SLIM_DCC3_PA0_MASK 0x00ffff1f
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#define SLIM_DCC3_PA0_WIDTH 24
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#define SLIM_DCC3_PA0_RESET 0000000000
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#define SLIM_DCC3_PA1 HW_REGISTER_RW( 0x7e210264 )
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#define SLIM_DCC3_PA1_MASK 0x00ffff3f
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#define SLIM_DCC3_PA1_WIDTH 24
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#define SLIM_DCC3_PA1_RESET 0000000000
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#define SLIM_DCC3_CON HW_REGISTER_RW( 0x7e210268 )
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#define SLIM_DCC3_CON_MASK 0xffff0073
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#define SLIM_DCC3_CON_WIDTH 32
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#define SLIM_DCC3_CON_RESET 0000000000
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#define SLIM_DCC3_STAT HW_REGISTER_RW( 0x7e21026c )
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#define SLIM_DCC3_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC3_STAT_WIDTH 32
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#define SLIM_DCC3_STAT_RESET 0000000000
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#define SLIM_DCC4_PA0 HW_REGISTER_RW( 0x7e210280 )
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#define SLIM_DCC4_PA0_MASK 0x00ffff1f
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#define SLIM_DCC4_PA0_WIDTH 24
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#define SLIM_DCC4_PA0_RESET 0000000000
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#define SLIM_DCC4_PA1 HW_REGISTER_RW( 0x7e210284 )
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#define SLIM_DCC4_PA1_MASK 0x00ffff3f
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#define SLIM_DCC4_PA1_WIDTH 24
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#define SLIM_DCC4_PA1_RESET 0000000000
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#define SLIM_DCC4_CON HW_REGISTER_RW( 0x7e210288 )
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#define SLIM_DCC4_CON_MASK 0xffff0073
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#define SLIM_DCC4_CON_WIDTH 32
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#define SLIM_DCC4_CON_RESET 0000000000
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#define SLIM_DCC4_STAT HW_REGISTER_RW( 0x7e21028c )
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#define SLIM_DCC4_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC4_STAT_WIDTH 32
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#define SLIM_DCC4_STAT_RESET 0000000000
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#define SLIM_DCC5_PA0 HW_REGISTER_RW( 0x7e2102a0 )
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#define SLIM_DCC5_PA0_MASK 0x00ffff1f
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#define SLIM_DCC5_PA0_WIDTH 24
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#define SLIM_DCC5_PA0_RESET 0000000000
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#define SLIM_DCC5_PA1 HW_REGISTER_RW( 0x7e2102a4 )
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#define SLIM_DCC5_PA1_MASK 0x00ffff3f
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#define SLIM_DCC5_PA1_WIDTH 24
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#define SLIM_DCC5_PA1_RESET 0000000000
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#define SLIM_DCC5_CON HW_REGISTER_RW( 0x7e2102a8 )
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#define SLIM_DCC5_CON_MASK 0xffff0073
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#define SLIM_DCC5_CON_WIDTH 32
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#define SLIM_DCC5_CON_RESET 0000000000
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#define SLIM_DCC5_STAT HW_REGISTER_RW( 0x7e2102ac )
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#define SLIM_DCC5_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC5_STAT_WIDTH 32
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#define SLIM_DCC5_STAT_RESET 0000000000
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#define SLIM_DCC6_PA0 HW_REGISTER_RW( 0x7e2102c0 )
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#define SLIM_DCC6_PA0_MASK 0x00ffff1f
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#define SLIM_DCC6_PA0_WIDTH 24
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#define SLIM_DCC6_PA0_RESET 0000000000
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#define SLIM_DCC6_PA1 HW_REGISTER_RW( 0x7e2102c4 )
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#define SLIM_DCC6_PA1_MASK 0x00ffff3f
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#define SLIM_DCC6_PA1_WIDTH 24
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#define SLIM_DCC6_PA1_RESET 0000000000
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#define SLIM_DCC6_CON HW_REGISTER_RW( 0x7e2102c8 )
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#define SLIM_DCC6_CON_MASK 0xffff0073
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#define SLIM_DCC6_CON_WIDTH 32
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#define SLIM_DCC6_CON_RESET 0000000000
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#define SLIM_DCC6_STAT HW_REGISTER_RW( 0x7e2102cc )
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#define SLIM_DCC6_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC6_STAT_WIDTH 32
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#define SLIM_DCC6_STAT_RESET 0000000000
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#define SLIM_DCC7_PA0 HW_REGISTER_RW( 0x7e2102e0 )
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#define SLIM_DCC7_PA0_MASK 0x00ffff1f
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#define SLIM_DCC7_PA0_WIDTH 24
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#define SLIM_DCC7_PA0_RESET 0000000000
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#define SLIM_DCC7_PA1 HW_REGISTER_RW( 0x7e2102e4 )
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#define SLIM_DCC7_PA1_MASK 0x00ffff3f
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#define SLIM_DCC7_PA1_WIDTH 24
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#define SLIM_DCC7_PA1_RESET 0000000000
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#define SLIM_DCC7_CON HW_REGISTER_RW( 0x7e2102e8 )
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#define SLIM_DCC7_CON_MASK 0xffff0073
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#define SLIM_DCC7_CON_WIDTH 32
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#define SLIM_DCC7_CON_RESET 0000000000
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#define SLIM_DCC7_STAT HW_REGISTER_RW( 0x7e2102ec )
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#define SLIM_DCC7_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC7_STAT_WIDTH 32
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#define SLIM_DCC7_STAT_RESET 0000000000
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#define SLIM_DCC8_PA0 HW_REGISTER_RW( 0x7e210300 )
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#define SLIM_DCC8_PA0_MASK 0x00ffff1f
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#define SLIM_DCC8_PA0_WIDTH 24
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#define SLIM_DCC8_PA0_RESET 0000000000
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#define SLIM_DCC8_PA1 HW_REGISTER_RW( 0x7e210304 )
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#define SLIM_DCC8_PA1_MASK 0x00ffff3f
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#define SLIM_DCC8_PA1_WIDTH 24
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#define SLIM_DCC8_PA1_RESET 0000000000
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#define SLIM_DCC8_CON HW_REGISTER_RW( 0x7e210308 )
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#define SLIM_DCC8_CON_MASK 0xffff0073
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#define SLIM_DCC8_CON_WIDTH 32
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#define SLIM_DCC8_CON_RESET 0000000000
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#define SLIM_DCC8_STAT HW_REGISTER_RW( 0x7e21030c )
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#define SLIM_DCC8_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC8_STAT_WIDTH 32
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#define SLIM_DCC8_STAT_RESET 0000000000
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#define SLIM_DCC9_PA0 HW_REGISTER_RW( 0x7e210320 )
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#define SLIM_DCC9_PA0_MASK 0x00ffff1f
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#define SLIM_DCC9_PA0_WIDTH 24
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#define SLIM_DCC9_PA0_RESET 0000000000
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#define SLIM_DCC9_PA1 HW_REGISTER_RW( 0x7e210324 )
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#define SLIM_DCC9_PA1_MASK 0x00ffff3f
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#define SLIM_DCC9_PA1_WIDTH 24
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#define SLIM_DCC9_PA1_RESET 0000000000
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#define SLIM_DCC9_CON HW_REGISTER_RW( 0x7e210328 )
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#define SLIM_DCC9_CON_MASK 0xffff0073
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#define SLIM_DCC9_CON_WIDTH 32
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#define SLIM_DCC9_CON_RESET 0000000000
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#define SLIM_DCC9_STAT HW_REGISTER_RW( 0x7e21032c )
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#define SLIM_DCC9_STAT_MASK 0xc0ff00c7
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#define SLIM_DCC9_STAT_WIDTH 32
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#define SLIM_DCC9_STAT_RESET 0000000000
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