651 lines
46 KiB
C
Executable File
651 lines
46 KiB
C
Executable File
// This file was generated by the create_regs script
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#define SMI_BASE 0x7e600000
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#define SMI_APB_ID 0x534d4958
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#define SMI_CS HW_REGISTER_RW( 0x7e600000 )
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#define SMI_CS_MASK 0xff00ffff
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#define SMI_CS_WIDTH 32
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#define SMI_CS_RXF_BITS 31:31
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#define SMI_CS_RXF_SET 0x80000000
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#define SMI_CS_RXF_CLR 0x7fffffff
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#define SMI_CS_RXF_MSB 31
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#define SMI_CS_RXF_LSB 31
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#define SMI_CS_RXF_RESET 0x0
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#define SMI_CS_TXE_BITS 30:30
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#define SMI_CS_TXE_SET 0x40000000
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#define SMI_CS_TXE_CLR 0xbfffffff
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#define SMI_CS_TXE_MSB 30
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#define SMI_CS_TXE_LSB 30
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#define SMI_CS_TXE_RESET 0x1
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#define SMI_CS_RXD_BITS 29:29
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#define SMI_CS_RXD_SET 0x20000000
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#define SMI_CS_RXD_CLR 0xdfffffff
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#define SMI_CS_RXD_MSB 29
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#define SMI_CS_RXD_LSB 29
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#define SMI_CS_RXD_RESET 0x0
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#define SMI_CS_TXD_BITS 28:28
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#define SMI_CS_TXD_SET 0x10000000
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#define SMI_CS_TXD_CLR 0xefffffff
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#define SMI_CS_TXD_MSB 28
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#define SMI_CS_TXD_LSB 28
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#define SMI_CS_TXD_RESET 0x1
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#define SMI_CS_RXR_BITS 27:27
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#define SMI_CS_RXR_SET 0x08000000
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#define SMI_CS_RXR_CLR 0xf7ffffff
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#define SMI_CS_RXR_MSB 27
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#define SMI_CS_RXR_LSB 27
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#define SMI_CS_RXR_RESET 0x0
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#define SMI_CS_TXW_BITS 26:26
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#define SMI_CS_TXW_SET 0x04000000
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#define SMI_CS_TXW_CLR 0xfbffffff
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#define SMI_CS_TXW_MSB 26
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#define SMI_CS_TXW_LSB 26
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#define SMI_CS_TXW_RESET 0x1
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#define SMI_CS_AFERR_BITS 25:25
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#define SMI_CS_AFERR_SET 0x02000000
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#define SMI_CS_AFERR_CLR 0xfdffffff
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#define SMI_CS_AFERR_MSB 25
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#define SMI_CS_AFERR_LSB 25
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#define SMI_CS_AFERR_RESET 0x0
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#define SMI_CS_PRDY_BITS 24:24
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#define SMI_CS_PRDY_SET 0x01000000
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#define SMI_CS_PRDY_CLR 0xfeffffff
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#define SMI_CS_PRDY_MSB 24
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#define SMI_CS_PRDY_LSB 24
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#define SMI_CS_PRDY_RESET 0x0
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#define SMI_CS_EDREQ_BITS 15:15
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#define SMI_CS_EDREQ_SET 0x00008000
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#define SMI_CS_EDREQ_CLR 0xffff7fff
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#define SMI_CS_EDREQ_MSB 15
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#define SMI_CS_EDREQ_LSB 15
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#define SMI_CS_EDREQ_RESET 0x0
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#define SMI_CS_PXLDAT_BITS 14:14
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#define SMI_CS_PXLDAT_SET 0x00004000
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#define SMI_CS_PXLDAT_CLR 0xffffbfff
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#define SMI_CS_PXLDAT_MSB 14
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#define SMI_CS_PXLDAT_LSB 14
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#define SMI_CS_PXLDAT_RESET 0x0
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#define SMI_CS_SETERR_BITS 13:13
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#define SMI_CS_SETERR_SET 0x00002000
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#define SMI_CS_SETERR_CLR 0xffffdfff
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#define SMI_CS_SETERR_MSB 13
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#define SMI_CS_SETERR_LSB 13
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#define SMI_CS_SETERR_RESET 0x0
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#define SMI_CS_PVMODE_BITS 12:12
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#define SMI_CS_PVMODE_SET 0x00001000
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#define SMI_CS_PVMODE_CLR 0xffffefff
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#define SMI_CS_PVMODE_MSB 12
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#define SMI_CS_PVMODE_LSB 12
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#define SMI_CS_PVMODE_RESET 0x0
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#define SMI_CS_INTR_BITS 11:11
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#define SMI_CS_INTR_SET 0x00000800
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#define SMI_CS_INTR_CLR 0xfffff7ff
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#define SMI_CS_INTR_MSB 11
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#define SMI_CS_INTR_LSB 11
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#define SMI_CS_INTR_RESET 0x0
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#define SMI_CS_INTT_BITS 10:10
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#define SMI_CS_INTT_SET 0x00000400
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#define SMI_CS_INTT_CLR 0xfffffbff
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#define SMI_CS_INTT_MSB 10
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#define SMI_CS_INTT_LSB 10
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#define SMI_CS_INTT_RESET 0x0
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#define SMI_CS_INTD_BITS 9:9
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#define SMI_CS_INTD_SET 0x00000200
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#define SMI_CS_INTD_CLR 0xfffffdff
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#define SMI_CS_INTD_MSB 9
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#define SMI_CS_INTD_LSB 9
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#define SMI_CS_INTD_RESET 0x0
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#define SMI_CS_TEEN_BITS 8:8
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#define SMI_CS_TEEN_SET 0x00000100
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#define SMI_CS_TEEN_CLR 0xfffffeff
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#define SMI_CS_TEEN_MSB 8
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#define SMI_CS_TEEN_LSB 8
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#define SMI_CS_TEEN_RESET 0x0
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#define SMI_CS_PAD_BITS 7:6
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#define SMI_CS_PAD_SET 0x000000c0
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#define SMI_CS_PAD_CLR 0xffffff3f
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#define SMI_CS_PAD_MSB 7
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#define SMI_CS_PAD_LSB 6
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#define SMI_CS_PAD_RESET 0x0
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#define SMI_CS_WRITE_BITS 5:5
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#define SMI_CS_WRITE_SET 0x00000020
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#define SMI_CS_WRITE_CLR 0xffffffdf
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#define SMI_CS_WRITE_MSB 5
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#define SMI_CS_WRITE_LSB 5
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#define SMI_CS_WRITE_RESET 0x0
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#define SMI_CS_CLEAR_BITS 4:4
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#define SMI_CS_CLEAR_SET 0x00000010
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#define SMI_CS_CLEAR_CLR 0xffffffef
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#define SMI_CS_CLEAR_MSB 4
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#define SMI_CS_CLEAR_LSB 4
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#define SMI_CS_CLEAR_RESET 0x0
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#define SMI_CS_START_BITS 3:3
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#define SMI_CS_START_SET 0x00000008
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#define SMI_CS_START_CLR 0xfffffff7
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#define SMI_CS_START_MSB 3
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#define SMI_CS_START_LSB 3
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#define SMI_CS_START_RESET 0x0
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#define SMI_CS_ACTIVE_BITS 2:2
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#define SMI_CS_ACTIVE_SET 0x00000004
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#define SMI_CS_ACTIVE_CLR 0xfffffffb
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#define SMI_CS_ACTIVE_MSB 2
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#define SMI_CS_ACTIVE_LSB 2
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#define SMI_CS_ACTIVE_RESET 0x0
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#define SMI_CS_DONE_BITS 1:1
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#define SMI_CS_DONE_SET 0x00000002
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#define SMI_CS_DONE_CLR 0xfffffffd
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#define SMI_CS_DONE_MSB 1
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#define SMI_CS_DONE_LSB 1
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#define SMI_CS_DONE_RESET 0x0
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#define SMI_CS_ENABLE_BITS 0:0
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#define SMI_CS_ENABLE_SET 0x00000001
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#define SMI_CS_ENABLE_CLR 0xfffffffe
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#define SMI_CS_ENABLE_MSB 0
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#define SMI_CS_ENABLE_LSB 0
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#define SMI_CS_ENABLE_RESET 0x0
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#define SMI_L HW_REGISTER_RW( 0x7e600004 )
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#define SMI_L_MASK 0xffffffff
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#define SMI_L_WIDTH 32
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#define SMI_L_RESET 0000000000
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#define SMI_A HW_REGISTER_RW( 0x7e600008 )
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#define SMI_A_MASK 0x0000033f
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#define SMI_A_WIDTH 10
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#define SMI_A_RESET 0000000000
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#define SMI_A_DEVICE_BITS 9:8
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#define SMI_A_DEVICE_SET 0x00000300
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#define SMI_A_DEVICE_CLR 0xfffffcff
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#define SMI_A_DEVICE_MSB 9
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#define SMI_A_DEVICE_LSB 8
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#define SMI_A_ADDR_BITS 5:0
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#define SMI_A_ADDR_SET 0x0000003f
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#define SMI_A_ADDR_CLR 0xffffffc0
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#define SMI_A_ADDR_MSB 5
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#define SMI_A_ADDR_LSB 0
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#define SMI_D HW_REGISTER_RW( 0x7e60000c )
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#define SMI_D_MASK 0xffffffff
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#define SMI_D_WIDTH 32
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#define SMI_D_RESET 0000000000
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#define SMI_DSR0 HW_REGISTER_RW( 0x7e600010 )
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#define SMI_DSR0_MASK 0xffffffff
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#define SMI_DSR0_WIDTH 32
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#define SMI_DSR0_RESET 0x0101000c
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#define SMI_DSR0_RWIDTH_BITS 31:30
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#define SMI_DSR0_RWIDTH_SET 0xc0000000
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#define SMI_DSR0_RWIDTH_CLR 0x3fffffff
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#define SMI_DSR0_RWIDTH_MSB 31
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#define SMI_DSR0_RWIDTH_LSB 30
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#define SMI_DSR0_RSETUP_BITS 29:24
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#define SMI_DSR0_RSETUP_SET 0x3f000000
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#define SMI_DSR0_RSETUP_CLR 0xc0ffffff
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#define SMI_DSR0_RSETUP_MSB 29
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#define SMI_DSR0_RSETUP_LSB 24
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#define SMI_DSR0_MODE68_BITS 23:23
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#define SMI_DSR0_MODE68_SET 0x00800000
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#define SMI_DSR0_MODE68_CLR 0xff7fffff
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#define SMI_DSR0_MODE68_MSB 23
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#define SMI_DSR0_MODE68_LSB 23
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#define SMI_DSR0_FSETUP_BITS 22:22
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#define SMI_DSR0_FSETUP_SET 0x00400000
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#define SMI_DSR0_FSETUP_CLR 0xffbfffff
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#define SMI_DSR0_FSETUP_MSB 22
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#define SMI_DSR0_FSETUP_LSB 22
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#define SMI_DSR0_RHOLD_BITS 21:16
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#define SMI_DSR0_RHOLD_SET 0x003f0000
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#define SMI_DSR0_RHOLD_CLR 0xffc0ffff
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#define SMI_DSR0_RHOLD_MSB 21
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#define SMI_DSR0_RHOLD_LSB 16
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#define SMI_DSR0_RPACEALL_BITS 15:15
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#define SMI_DSR0_RPACEALL_SET 0x00008000
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#define SMI_DSR0_RPACEALL_CLR 0xffff7fff
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#define SMI_DSR0_RPACEALL_MSB 15
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#define SMI_DSR0_RPACEALL_LSB 15
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#define SMI_DSR0_RPACE_BITS 14:8
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#define SMI_DSR0_RPACE_SET 0x00007f00
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#define SMI_DSR0_RPACE_CLR 0xffff80ff
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#define SMI_DSR0_RPACE_MSB 14
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#define SMI_DSR0_RPACE_LSB 8
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#define SMI_DSR0_RDREQ_BITS 7:7
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#define SMI_DSR0_RDREQ_SET 0x00000080
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#define SMI_DSR0_RDREQ_CLR 0xffffff7f
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#define SMI_DSR0_RDREQ_MSB 7
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#define SMI_DSR0_RDREQ_LSB 7
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#define SMI_DSR0_RSTROBE_BITS 6:0
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#define SMI_DSR0_RSTROBE_SET 0x0000007f
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#define SMI_DSR0_RSTROBE_CLR 0xffffff80
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#define SMI_DSR0_RSTROBE_MSB 6
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#define SMI_DSR0_RSTROBE_LSB 0
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#define SMI_DSW0 HW_REGISTER_RW( 0x7e600014 )
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#define SMI_DSW0_MASK 0xffffffff
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#define SMI_DSW0_WIDTH 32
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#define SMI_DSW0_RESET 0x0101000c
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#define SMI_DSW0_WWIDTH_BITS 31:30
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#define SMI_DSW0_WWIDTH_SET 0xc0000000
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#define SMI_DSW0_WWIDTH_CLR 0x3fffffff
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#define SMI_DSW0_WWIDTH_MSB 31
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#define SMI_DSW0_WWIDTH_LSB 30
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#define SMI_DSW0_WSETUP_BITS 29:24
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#define SMI_DSW0_WSETUP_SET 0x3f000000
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#define SMI_DSW0_WSETUP_CLR 0xc0ffffff
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#define SMI_DSW0_WSETUP_MSB 29
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#define SMI_DSW0_WSETUP_LSB 24
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#define SMI_DSW0_WFORMAT_BITS 23:23
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#define SMI_DSW0_WFORMAT_SET 0x00800000
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#define SMI_DSW0_WFORMAT_CLR 0xff7fffff
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#define SMI_DSW0_WFORMAT_MSB 23
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#define SMI_DSW0_WFORMAT_LSB 23
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#define SMI_DSW0_WSWAP_BITS 22:22
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#define SMI_DSW0_WSWAP_SET 0x00400000
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#define SMI_DSW0_WSWAP_CLR 0xffbfffff
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#define SMI_DSW0_WSWAP_MSB 22
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#define SMI_DSW0_WSWAP_LSB 22
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#define SMI_DSW0_WHOLD_BITS 21:16
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#define SMI_DSW0_WHOLD_SET 0x003f0000
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#define SMI_DSW0_WHOLD_CLR 0xffc0ffff
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#define SMI_DSW0_WHOLD_MSB 21
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#define SMI_DSW0_WHOLD_LSB 16
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#define SMI_DSW0_WPACEALL_BITS 15:15
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#define SMI_DSW0_WPACEALL_SET 0x00008000
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#define SMI_DSW0_WPACEALL_CLR 0xffff7fff
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#define SMI_DSW0_WPACEALL_MSB 15
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#define SMI_DSW0_WPACEALL_LSB 15
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#define SMI_DSW0_WPACE_BITS 14:8
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#define SMI_DSW0_WPACE_SET 0x00007f00
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#define SMI_DSW0_WPACE_CLR 0xffff80ff
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#define SMI_DSW0_WPACE_MSB 14
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#define SMI_DSW0_WPACE_LSB 8
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#define SMI_DSW0_WDREQ_BITS 7:7
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#define SMI_DSW0_WDREQ_SET 0x00000080
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#define SMI_DSW0_WDREQ_CLR 0xffffff7f
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#define SMI_DSW0_WDREQ_MSB 7
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#define SMI_DSW0_WDREQ_LSB 7
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#define SMI_DSW0_WSTROBE_BITS 6:0
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#define SMI_DSW0_WSTROBE_SET 0x0000007f
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#define SMI_DSW0_WSTROBE_CLR 0xffffff80
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#define SMI_DSW0_WSTROBE_MSB 6
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#define SMI_DSW0_WSTROBE_LSB 0
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#define SMI_DSR1 HW_REGISTER_RW( 0x7e600018 )
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#define SMI_DSR1_MASK 0xffffffff
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#define SMI_DSR1_WIDTH 32
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#define SMI_DSR1_RESET 0x0101000c
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#define SMI_DSR1_RWIDTH_BITS 31:30
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#define SMI_DSR1_RWIDTH_SET 0xc0000000
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#define SMI_DSR1_RWIDTH_CLR 0x3fffffff
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#define SMI_DSR1_RWIDTH_MSB 31
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#define SMI_DSR1_RWIDTH_LSB 30
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#define SMI_DSR1_RSETUP_BITS 29:24
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#define SMI_DSR1_RSETUP_SET 0x3f000000
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#define SMI_DSR1_RSETUP_CLR 0xc0ffffff
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#define SMI_DSR1_RSETUP_MSB 29
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#define SMI_DSR1_RSETUP_LSB 24
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#define SMI_DSR1_MODE68_BITS 23:23
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#define SMI_DSR1_MODE68_SET 0x00800000
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#define SMI_DSR1_MODE68_CLR 0xff7fffff
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#define SMI_DSR1_MODE68_MSB 23
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#define SMI_DSR1_MODE68_LSB 23
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#define SMI_DSR1_FSETUP_BITS 22:22
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#define SMI_DSR1_FSETUP_SET 0x00400000
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#define SMI_DSR1_FSETUP_CLR 0xffbfffff
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#define SMI_DSR1_FSETUP_MSB 22
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#define SMI_DSR1_FSETUP_LSB 22
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#define SMI_DSR1_RHOLD_BITS 21:16
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#define SMI_DSR1_RHOLD_SET 0x003f0000
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#define SMI_DSR1_RHOLD_CLR 0xffc0ffff
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#define SMI_DSR1_RHOLD_MSB 21
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#define SMI_DSR1_RHOLD_LSB 16
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#define SMI_DSR1_RPACEALL_BITS 15:15
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#define SMI_DSR1_RPACEALL_SET 0x00008000
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#define SMI_DSR1_RPACEALL_CLR 0xffff7fff
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#define SMI_DSR1_RPACEALL_MSB 15
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#define SMI_DSR1_RPACEALL_LSB 15
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#define SMI_DSR1_RPACE_BITS 14:8
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#define SMI_DSR1_RPACE_SET 0x00007f00
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#define SMI_DSR1_RPACE_CLR 0xffff80ff
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#define SMI_DSR1_RPACE_MSB 14
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#define SMI_DSR1_RPACE_LSB 8
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#define SMI_DSR1_RDREQ_BITS 7:7
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#define SMI_DSR1_RDREQ_SET 0x00000080
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#define SMI_DSR1_RDREQ_CLR 0xffffff7f
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#define SMI_DSR1_RDREQ_MSB 7
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#define SMI_DSR1_RDREQ_LSB 7
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#define SMI_DSR1_RSTROBE_BITS 6:0
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#define SMI_DSR1_RSTROBE_SET 0x0000007f
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#define SMI_DSR1_RSTROBE_CLR 0xffffff80
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#define SMI_DSR1_RSTROBE_MSB 6
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#define SMI_DSR1_RSTROBE_LSB 0
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#define SMI_DSW1 HW_REGISTER_RW( 0x7e60001c )
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#define SMI_DSW1_MASK 0xffffffff
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#define SMI_DSW1_WIDTH 32
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#define SMI_DSW1_RESET 0x0101000c
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#define SMI_DSW1_WWIDTH_BITS 31:30
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#define SMI_DSW1_WWIDTH_SET 0xc0000000
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#define SMI_DSW1_WWIDTH_CLR 0x3fffffff
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#define SMI_DSW1_WWIDTH_MSB 31
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#define SMI_DSW1_WWIDTH_LSB 30
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#define SMI_DSW1_WSETUP_BITS 29:24
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#define SMI_DSW1_WSETUP_SET 0x3f000000
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#define SMI_DSW1_WSETUP_CLR 0xc0ffffff
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#define SMI_DSW1_WSETUP_MSB 29
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#define SMI_DSW1_WSETUP_LSB 24
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#define SMI_DSW1_WFORMAT_BITS 23:23
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#define SMI_DSW1_WFORMAT_SET 0x00800000
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#define SMI_DSW1_WFORMAT_CLR 0xff7fffff
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#define SMI_DSW1_WFORMAT_MSB 23
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#define SMI_DSW1_WFORMAT_LSB 23
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#define SMI_DSW1_WSWAP_BITS 22:22
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#define SMI_DSW1_WSWAP_SET 0x00400000
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#define SMI_DSW1_WSWAP_CLR 0xffbfffff
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#define SMI_DSW1_WSWAP_MSB 22
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#define SMI_DSW1_WSWAP_LSB 22
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#define SMI_DSW1_WHOLD_BITS 21:16
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#define SMI_DSW1_WHOLD_SET 0x003f0000
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#define SMI_DSW1_WHOLD_CLR 0xffc0ffff
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#define SMI_DSW1_WHOLD_MSB 21
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#define SMI_DSW1_WHOLD_LSB 16
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#define SMI_DSW1_WPACEALL_BITS 15:15
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#define SMI_DSW1_WPACEALL_SET 0x00008000
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#define SMI_DSW1_WPACEALL_CLR 0xffff7fff
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#define SMI_DSW1_WPACEALL_MSB 15
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#define SMI_DSW1_WPACEALL_LSB 15
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#define SMI_DSW1_WPACE_BITS 14:8
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#define SMI_DSW1_WPACE_SET 0x00007f00
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#define SMI_DSW1_WPACE_CLR 0xffff80ff
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#define SMI_DSW1_WPACE_MSB 14
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#define SMI_DSW1_WPACE_LSB 8
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#define SMI_DSW1_WDREQ_BITS 7:7
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#define SMI_DSW1_WDREQ_SET 0x00000080
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#define SMI_DSW1_WDREQ_CLR 0xffffff7f
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#define SMI_DSW1_WDREQ_MSB 7
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#define SMI_DSW1_WDREQ_LSB 7
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#define SMI_DSW1_WSTROBE_BITS 6:0
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#define SMI_DSW1_WSTROBE_SET 0x0000007f
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#define SMI_DSW1_WSTROBE_CLR 0xffffff80
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#define SMI_DSW1_WSTROBE_MSB 6
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#define SMI_DSW1_WSTROBE_LSB 0
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#define SMI_DSR2 HW_REGISTER_RW( 0x7e600020 )
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#define SMI_DSR2_MASK 0xffffffff
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#define SMI_DSR2_WIDTH 32
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#define SMI_DSR2_RESET 0x0101000c
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#define SMI_DSR2_RWIDTH_BITS 31:30
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#define SMI_DSR2_RWIDTH_SET 0xc0000000
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#define SMI_DSR2_RWIDTH_CLR 0x3fffffff
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#define SMI_DSR2_RWIDTH_MSB 31
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#define SMI_DSR2_RWIDTH_LSB 30
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#define SMI_DSR2_RSETUP_BITS 29:24
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#define SMI_DSR2_RSETUP_SET 0x3f000000
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#define SMI_DSR2_RSETUP_CLR 0xc0ffffff
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#define SMI_DSR2_RSETUP_MSB 29
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#define SMI_DSR2_RSETUP_LSB 24
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#define SMI_DSR2_MODE68_BITS 23:23
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#define SMI_DSR2_MODE68_SET 0x00800000
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#define SMI_DSR2_MODE68_CLR 0xff7fffff
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#define SMI_DSR2_MODE68_MSB 23
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#define SMI_DSR2_MODE68_LSB 23
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#define SMI_DSR2_FSETUP_BITS 22:22
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#define SMI_DSR2_FSETUP_SET 0x00400000
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#define SMI_DSR2_FSETUP_CLR 0xffbfffff
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#define SMI_DSR2_FSETUP_MSB 22
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#define SMI_DSR2_FSETUP_LSB 22
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#define SMI_DSR2_RHOLD_BITS 21:16
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#define SMI_DSR2_RHOLD_SET 0x003f0000
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#define SMI_DSR2_RHOLD_CLR 0xffc0ffff
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#define SMI_DSR2_RHOLD_MSB 21
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#define SMI_DSR2_RHOLD_LSB 16
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#define SMI_DSR2_RPACEALL_BITS 15:15
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#define SMI_DSR2_RPACEALL_SET 0x00008000
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#define SMI_DSR2_RPACEALL_CLR 0xffff7fff
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#define SMI_DSR2_RPACEALL_MSB 15
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#define SMI_DSR2_RPACEALL_LSB 15
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#define SMI_DSR2_RPACE_BITS 14:8
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#define SMI_DSR2_RPACE_SET 0x00007f00
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#define SMI_DSR2_RPACE_CLR 0xffff80ff
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#define SMI_DSR2_RPACE_MSB 14
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#define SMI_DSR2_RPACE_LSB 8
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#define SMI_DSR2_RDREQ_BITS 7:7
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#define SMI_DSR2_RDREQ_SET 0x00000080
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#define SMI_DSR2_RDREQ_CLR 0xffffff7f
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#define SMI_DSR2_RDREQ_MSB 7
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#define SMI_DSR2_RDREQ_LSB 7
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#define SMI_DSR2_RSTROBE_BITS 6:0
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#define SMI_DSR2_RSTROBE_SET 0x0000007f
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#define SMI_DSR2_RSTROBE_CLR 0xffffff80
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#define SMI_DSR2_RSTROBE_MSB 6
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#define SMI_DSR2_RSTROBE_LSB 0
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#define SMI_DSW2 HW_REGISTER_RW( 0x7e600024 )
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#define SMI_DSW2_MASK 0xffffffff
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#define SMI_DSW2_WIDTH 32
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#define SMI_DSW2_RESET 0x0101000c
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#define SMI_DSW2_WWIDTH_BITS 31:30
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#define SMI_DSW2_WWIDTH_SET 0xc0000000
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#define SMI_DSW2_WWIDTH_CLR 0x3fffffff
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#define SMI_DSW2_WWIDTH_MSB 31
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#define SMI_DSW2_WWIDTH_LSB 30
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#define SMI_DSW2_WSETUP_BITS 29:24
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#define SMI_DSW2_WSETUP_SET 0x3f000000
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#define SMI_DSW2_WSETUP_CLR 0xc0ffffff
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#define SMI_DSW2_WSETUP_MSB 29
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#define SMI_DSW2_WSETUP_LSB 24
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#define SMI_DSW2_WFORMAT_BITS 23:23
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#define SMI_DSW2_WFORMAT_SET 0x00800000
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#define SMI_DSW2_WFORMAT_CLR 0xff7fffff
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#define SMI_DSW2_WFORMAT_MSB 23
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#define SMI_DSW2_WFORMAT_LSB 23
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#define SMI_DSW2_WSWAP_BITS 22:22
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#define SMI_DSW2_WSWAP_SET 0x00400000
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#define SMI_DSW2_WSWAP_CLR 0xffbfffff
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#define SMI_DSW2_WSWAP_MSB 22
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#define SMI_DSW2_WSWAP_LSB 22
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#define SMI_DSW2_WHOLD_BITS 21:16
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#define SMI_DSW2_WHOLD_SET 0x003f0000
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#define SMI_DSW2_WHOLD_CLR 0xffc0ffff
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#define SMI_DSW2_WHOLD_MSB 21
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#define SMI_DSW2_WHOLD_LSB 16
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#define SMI_DSW2_WPACEALL_BITS 15:15
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#define SMI_DSW2_WPACEALL_SET 0x00008000
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#define SMI_DSW2_WPACEALL_CLR 0xffff7fff
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#define SMI_DSW2_WPACEALL_MSB 15
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#define SMI_DSW2_WPACEALL_LSB 15
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#define SMI_DSW2_WPACE_BITS 14:8
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#define SMI_DSW2_WPACE_SET 0x00007f00
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#define SMI_DSW2_WPACE_CLR 0xffff80ff
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#define SMI_DSW2_WPACE_MSB 14
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#define SMI_DSW2_WPACE_LSB 8
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#define SMI_DSW2_WDREQ_BITS 7:7
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#define SMI_DSW2_WDREQ_SET 0x00000080
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#define SMI_DSW2_WDREQ_CLR 0xffffff7f
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#define SMI_DSW2_WDREQ_MSB 7
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#define SMI_DSW2_WDREQ_LSB 7
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#define SMI_DSW2_WSTROBE_BITS 6:0
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#define SMI_DSW2_WSTROBE_SET 0x0000007f
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#define SMI_DSW2_WSTROBE_CLR 0xffffff80
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#define SMI_DSW2_WSTROBE_MSB 6
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#define SMI_DSW2_WSTROBE_LSB 0
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#define SMI_DSR3 HW_REGISTER_RW( 0x7e600028 )
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#define SMI_DSR3_MASK 0xffffffff
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#define SMI_DSR3_WIDTH 32
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#define SMI_DSR3_RESET 0x0101000c
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#define SMI_DSR3_RWIDTH_BITS 31:30
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#define SMI_DSR3_RWIDTH_SET 0xc0000000
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#define SMI_DSR3_RWIDTH_CLR 0x3fffffff
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#define SMI_DSR3_RWIDTH_MSB 31
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#define SMI_DSR3_RWIDTH_LSB 30
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#define SMI_DSR3_RSETUP_BITS 29:24
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#define SMI_DSR3_RSETUP_SET 0x3f000000
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#define SMI_DSR3_RSETUP_CLR 0xc0ffffff
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#define SMI_DSR3_RSETUP_MSB 29
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#define SMI_DSR3_RSETUP_LSB 24
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#define SMI_DSR3_MODE68_BITS 23:23
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#define SMI_DSR3_MODE68_SET 0x00800000
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#define SMI_DSR3_MODE68_CLR 0xff7fffff
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#define SMI_DSR3_MODE68_MSB 23
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#define SMI_DSR3_MODE68_LSB 23
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#define SMI_DSR3_FSETUP_BITS 22:22
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#define SMI_DSR3_FSETUP_SET 0x00400000
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#define SMI_DSR3_FSETUP_CLR 0xffbfffff
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#define SMI_DSR3_FSETUP_MSB 22
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#define SMI_DSR3_FSETUP_LSB 22
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#define SMI_DSR3_RHOLD_BITS 21:16
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#define SMI_DSR3_RHOLD_SET 0x003f0000
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#define SMI_DSR3_RHOLD_CLR 0xffc0ffff
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#define SMI_DSR3_RHOLD_MSB 21
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#define SMI_DSR3_RHOLD_LSB 16
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#define SMI_DSR3_RPACEALL_BITS 15:15
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#define SMI_DSR3_RPACEALL_SET 0x00008000
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#define SMI_DSR3_RPACEALL_CLR 0xffff7fff
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#define SMI_DSR3_RPACEALL_MSB 15
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#define SMI_DSR3_RPACEALL_LSB 15
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#define SMI_DSR3_RPACE_BITS 14:8
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#define SMI_DSR3_RPACE_SET 0x00007f00
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#define SMI_DSR3_RPACE_CLR 0xffff80ff
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#define SMI_DSR3_RPACE_MSB 14
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#define SMI_DSR3_RPACE_LSB 8
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#define SMI_DSR3_RDREQ_BITS 7:7
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#define SMI_DSR3_RDREQ_SET 0x00000080
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#define SMI_DSR3_RDREQ_CLR 0xffffff7f
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#define SMI_DSR3_RDREQ_MSB 7
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#define SMI_DSR3_RDREQ_LSB 7
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#define SMI_DSR3_RSTROBE_BITS 6:0
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#define SMI_DSR3_RSTROBE_SET 0x0000007f
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#define SMI_DSR3_RSTROBE_CLR 0xffffff80
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#define SMI_DSR3_RSTROBE_MSB 6
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#define SMI_DSR3_RSTROBE_LSB 0
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#define SMI_DSW3 HW_REGISTER_RW( 0x7e60002c )
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#define SMI_DSW3_MASK 0xffffffff
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#define SMI_DSW3_WIDTH 32
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#define SMI_DSW3_RESET 0x0101000c
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#define SMI_DSW3_WWIDTH_BITS 31:30
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#define SMI_DSW3_WWIDTH_SET 0xc0000000
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#define SMI_DSW3_WWIDTH_CLR 0x3fffffff
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#define SMI_DSW3_WWIDTH_MSB 31
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#define SMI_DSW3_WWIDTH_LSB 30
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#define SMI_DSW3_WSETUP_BITS 29:24
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#define SMI_DSW3_WSETUP_SET 0x3f000000
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#define SMI_DSW3_WSETUP_CLR 0xc0ffffff
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#define SMI_DSW3_WSETUP_MSB 29
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#define SMI_DSW3_WSETUP_LSB 24
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#define SMI_DSW3_WFORMAT_BITS 23:23
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#define SMI_DSW3_WFORMAT_SET 0x00800000
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#define SMI_DSW3_WFORMAT_CLR 0xff7fffff
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#define SMI_DSW3_WFORMAT_MSB 23
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#define SMI_DSW3_WFORMAT_LSB 23
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#define SMI_DSW3_WSWAP_BITS 22:22
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#define SMI_DSW3_WSWAP_SET 0x00400000
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#define SMI_DSW3_WSWAP_CLR 0xffbfffff
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#define SMI_DSW3_WSWAP_MSB 22
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#define SMI_DSW3_WSWAP_LSB 22
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#define SMI_DSW3_WHOLD_BITS 21:16
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#define SMI_DSW3_WHOLD_SET 0x003f0000
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#define SMI_DSW3_WHOLD_CLR 0xffc0ffff
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#define SMI_DSW3_WHOLD_MSB 21
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#define SMI_DSW3_WHOLD_LSB 16
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#define SMI_DSW3_WPACEALL_BITS 15:15
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#define SMI_DSW3_WPACEALL_SET 0x00008000
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#define SMI_DSW3_WPACEALL_CLR 0xffff7fff
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#define SMI_DSW3_WPACEALL_MSB 15
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#define SMI_DSW3_WPACEALL_LSB 15
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#define SMI_DSW3_WPACE_BITS 14:8
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#define SMI_DSW3_WPACE_SET 0x00007f00
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#define SMI_DSW3_WPACE_CLR 0xffff80ff
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#define SMI_DSW3_WPACE_MSB 14
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#define SMI_DSW3_WPACE_LSB 8
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#define SMI_DSW3_WDREQ_BITS 7:7
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#define SMI_DSW3_WDREQ_SET 0x00000080
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#define SMI_DSW3_WDREQ_CLR 0xffffff7f
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#define SMI_DSW3_WDREQ_MSB 7
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#define SMI_DSW3_WDREQ_LSB 7
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#define SMI_DSW3_WSTROBE_BITS 6:0
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#define SMI_DSW3_WSTROBE_SET 0x0000007f
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#define SMI_DSW3_WSTROBE_CLR 0xffffff80
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#define SMI_DSW3_WSTROBE_MSB 6
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#define SMI_DSW3_WSTROBE_LSB 0
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#define SMI_DC HW_REGISTER_RW( 0x7e600030 )
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#define SMI_DC_MASK 0x11ffffff
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#define SMI_DC_WIDTH 29
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#define SMI_DC_RESET 0x00c10820
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#define SMI_DC_DMAEN_BITS 28:28
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#define SMI_DC_DMAEN_SET 0x10000000
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#define SMI_DC_DMAEN_CLR 0xefffffff
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#define SMI_DC_DMAEN_MSB 28
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#define SMI_DC_DMAEN_LSB 28
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#define SMI_DC_DMAP_BITS 24:24
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#define SMI_DC_DMAP_SET 0x01000000
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#define SMI_DC_DMAP_CLR 0xfeffffff
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#define SMI_DC_DMAP_MSB 24
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#define SMI_DC_DMAP_LSB 24
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#define SMI_DC_PANICR_BITS 23:18
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#define SMI_DC_PANICR_SET 0x00fc0000
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#define SMI_DC_PANICR_CLR 0xff03ffff
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#define SMI_DC_PANICR_MSB 23
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#define SMI_DC_PANICR_LSB 18
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#define SMI_DC_PANICW_BITS 17:12
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#define SMI_DC_PANICW_SET 0x0003f000
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#define SMI_DC_PANICW_CLR 0xfffc0fff
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#define SMI_DC_PANICW_MSB 17
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#define SMI_DC_PANICW_LSB 12
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#define SMI_DC_REQR_BITS 11:6
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#define SMI_DC_REQR_SET 0x00000fc0
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#define SMI_DC_REQR_CLR 0xfffff03f
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#define SMI_DC_REQR_MSB 11
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#define SMI_DC_REQR_LSB 6
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#define SMI_DC_REQW_BITS 5:0
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#define SMI_DC_REQW_SET 0x0000003f
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#define SMI_DC_REQW_CLR 0xffffffc0
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#define SMI_DC_REQW_MSB 5
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#define SMI_DC_REQW_LSB 0
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#define SMI_DCS HW_REGISTER_RW( 0x7e600034 )
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#define SMI_DCS_MASK 0x0000000f
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#define SMI_DCS_WIDTH 4
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#define SMI_DCS_RESET 0000000000
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#define SMI_DCS_WRITE_BITS 3:3
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#define SMI_DCS_WRITE_SET 0x00000008
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#define SMI_DCS_WRITE_CLR 0xfffffff7
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#define SMI_DCS_WRITE_MSB 3
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#define SMI_DCS_WRITE_LSB 3
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#define SMI_DCS_DONE_BITS 2:2
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#define SMI_DCS_DONE_SET 0x00000004
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#define SMI_DCS_DONE_CLR 0xfffffffb
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#define SMI_DCS_DONE_MSB 2
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#define SMI_DCS_DONE_LSB 2
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#define SMI_DCS_START_BITS 1:1
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#define SMI_DCS_START_SET 0x00000002
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#define SMI_DCS_START_CLR 0xfffffffd
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#define SMI_DCS_START_MSB 1
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#define SMI_DCS_START_LSB 1
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#define SMI_DCS_EANBLE_BITS 0:0
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#define SMI_DCS_EANBLE_SET 0x00000001
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#define SMI_DCS_EANBLE_CLR 0xfffffffe
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#define SMI_DCS_EANBLE_MSB 0
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#define SMI_DCS_EANBLE_LSB 0
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#define SMI_DA HW_REGISTER_RW( 0x7e600038 )
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#define SMI_DA_MASK 0x0000033f
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#define SMI_DA_WIDTH 10
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#define SMI_DA_RESET 0000000000
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#define SMI_DA_WRITE_BITS 9:8
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#define SMI_DA_WRITE_SET 0x00000300
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#define SMI_DA_WRITE_CLR 0xfffffcff
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#define SMI_DA_WRITE_MSB 9
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#define SMI_DA_WRITE_LSB 8
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#define SMI_DA_ADDR_BITS 5:0
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#define SMI_DA_ADDR_SET 0x0000003f
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#define SMI_DA_ADDR_CLR 0xffffffc0
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#define SMI_DA_ADDR_MSB 5
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#define SMI_DA_ADDR_LSB 0
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#define SMI_DD HW_REGISTER_RW( 0x7e60003c )
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#define SMI_DD_MASK 0x0003ffff
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#define SMI_DD_WIDTH 18
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#define SMI_DD_RESET 0000000000
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#define SMI_FD HW_REGISTER_RW( 0x7e600040 )
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#define SMI_FD_MASK 0x00003f3f
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#define SMI_FD_WIDTH 14
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#define SMI_FD_RESET 0000000000
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#define SMI_FD_FLVL_BITS 13:8
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#define SMI_FD_FLVL_SET 0x00003f00
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#define SMI_FD_FLVL_CLR 0xffffc0ff
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#define SMI_FD_FLVL_MSB 13
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#define SMI_FD_FLVL_LSB 8
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#define SMI_FD_FLVL_RESET 0x0
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#define SMI_FD_FCNT_BITS 5:0
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#define SMI_FD_FCNT_SET 0x0000003f
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#define SMI_FD_FCNT_CLR 0xffffffc0
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#define SMI_FD_FCNT_MSB 5
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#define SMI_FD_FCNT_LSB 0
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#define SMI_FD_FCNT_RESET 0x0
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