108 lines
7.6 KiB
C
Executable File
108 lines
7.6 KiB
C
Executable File
// This file was generated by the create_regs script
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#define SPI_BASE 0x7e204000
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#define SPI_CS HW_REGISTER_RW( 0x7e204000 )
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#define SPI_CS_MASK 0x001f07ff
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#define SPI_CS_WIDTH 21
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#define SPI_CS_RESET 0000000000
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#define SPI_CS_RXF_BITS 20:20
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#define SPI_CS_RXF_SET 0x00100000
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#define SPI_CS_RXF_CLR 0xffefffff
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#define SPI_CS_RXF_MSB 20
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#define SPI_CS_RXF_LSB 20
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#define SPI_CS_RXR_BITS 19:19
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#define SPI_CS_RXR_SET 0x00080000
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#define SPI_CS_RXR_CLR 0xfff7ffff
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#define SPI_CS_RXR_MSB 19
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#define SPI_CS_RXR_LSB 19
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#define SPI_CS_TXD_BITS 18:18
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#define SPI_CS_TXD_SET 0x00040000
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#define SPI_CS_TXD_CLR 0xfffbffff
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#define SPI_CS_TXD_MSB 18
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#define SPI_CS_TXD_LSB 18
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#define SPI_CS_RXD_BITS 17:17
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#define SPI_CS_RXD_SET 0x00020000
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#define SPI_CS_RXD_CLR 0xfffdffff
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#define SPI_CS_RXD_MSB 17
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#define SPI_CS_RXD_LSB 17
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#define SPI_CS_DONE_BITS 16:16
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#define SPI_CS_DONE_SET 0x00010000
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#define SPI_CS_DONE_CLR 0xfffeffff
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#define SPI_CS_DONE_MSB 16
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#define SPI_CS_DONE_LSB 16
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#define SPI_CS_INTR_BITS 10:10
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#define SPI_CS_INTR_SET 0x00000400
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#define SPI_CS_INTR_CLR 0xfffffbff
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#define SPI_CS_INTR_MSB 10
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#define SPI_CS_INTR_LSB 10
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#define SPI_CS_INTD_BITS 9:9
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#define SPI_CS_INTD_SET 0x00000200
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#define SPI_CS_INTD_CLR 0xfffffdff
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#define SPI_CS_INTD_MSB 9
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#define SPI_CS_INTD_LSB 9
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#define SPI_CS_DMAEN_BITS 8:8
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#define SPI_CS_DMAEN_SET 0x00000100
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#define SPI_CS_DMAEN_CLR 0xfffffeff
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#define SPI_CS_DMAEN_MSB 8
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#define SPI_CS_DMAEN_LSB 8
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#define SPI_CS_TA_BITS 7:7
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#define SPI_CS_TA_SET 0x00000080
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#define SPI_CS_TA_CLR 0xffffff7f
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#define SPI_CS_TA_MSB 7
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#define SPI_CS_TA_LSB 7
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#define SPI_CS_CSPOL_BITS 6:6
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#define SPI_CS_CSPOL_SET 0x00000040
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#define SPI_CS_CSPOL_CLR 0xffffffbf
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#define SPI_CS_CSPOL_MSB 6
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#define SPI_CS_CSPOL_LSB 6
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#define SPI_CS_CLEAR_BITS 5:4
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#define SPI_CS_CLEAR_SET 0x00000030
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#define SPI_CS_CLEAR_CLR 0xffffffcf
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#define SPI_CS_CLEAR_MSB 5
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#define SPI_CS_CLEAR_LSB 4
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#define SPI_CS_CPOL_BITS 3:3
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#define SPI_CS_CPOL_SET 0x00000008
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#define SPI_CS_CPOL_CLR 0xfffffff7
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#define SPI_CS_CPOL_MSB 3
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#define SPI_CS_CPOL_LSB 3
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#define SPI_CS_CPHA_BITS 2:2
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#define SPI_CS_CPHA_SET 0x00000004
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#define SPI_CS_CPHA_CLR 0xfffffffb
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#define SPI_CS_CPHA_MSB 2
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#define SPI_CS_CPHA_LSB 2
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#define SPI_FIFO HW_REGISTER_RW( 0x7e204004 )
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#define SPI_FIFO_MASK 0x000000ff
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#define SPI_FIFO_WIDTH 8
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#define SPI_FIFO_RESET 0000000000
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#define SPI_FIFO_DATA_BITS 7:0
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#define SPI_FIFO_DATA_SET 0x000000ff
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#define SPI_FIFO_DATA_CLR 0xffffff00
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#define SPI_FIFO_DATA_MSB 7
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#define SPI_FIFO_DATA_LSB 0
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#define SPI_CLK HW_REGISTER_RW( 0x7e204008 )
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#define SPI_CLK_MASK 0x0000ffff
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#define SPI_CLK_WIDTH 16
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#define SPI_CLK_RESET 0000000000
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#define SPI_CLK_CDIV_BITS 15:0
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#define SPI_CLK_CDIV_SET 0x0000ffff
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#define SPI_CLK_CDIV_CLR 0xffff0000
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#define SPI_CLK_CDIV_MSB 15
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#define SPI_CLK_CDIV_LSB 0
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#define SPI_DLEN HW_REGISTER_RW( 0x7e20400c )
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#define SPI_DLEN_MASK 0x0000ffff
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#define SPI_DLEN_WIDTH 16
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#define SPI_DLEN_RESET 0000000000
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#define SPI_DLEN_LEN_BITS 15:0
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#define SPI_DLEN_LEN_SET 0x0000ffff
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#define SPI_DLEN_LEN_CLR 0xffff0000
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#define SPI_DLEN_LEN_MSB 15
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#define SPI_DLEN_LEN_LSB 0
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#define SPI_LTOH HW_REGISTER_RW( 0x7e204010 )
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#define SPI_LTOH_MASK 0x0000000f
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#define SPI_LTOH_WIDTH 4
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#define SPI_LTOH_RESET 0x00000001
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#define SPI_LTOH_TOH_BITS 3:0
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#define SPI_LTOH_TOH_SET 0x0000000f
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#define SPI_LTOH_TOH_CLR 0xfffffff0
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#define SPI_LTOH_TOH_MSB 3
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#define SPI_LTOH_TOH_LSB 0
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