438 lines
31 KiB
C
Executable File
438 lines
31 KiB
C
Executable File
// This file was generated by the create_regs script
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#define SYSAC_BASE 0x7e009000
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#define SYSAC_APB_ID 0x4152424d
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#define SYSAC_HOST_PRIORITY HW_REGISTER_RW( 0x7e009000 )
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#define SYSAC_HOST_PRIORITY_MASK 0x0000000f
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#define SYSAC_HOST_PRIORITY_WIDTH 4
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#define SYSAC_HOST_PRIORITY_RESET 0000000000
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#define SYSAC_HOST_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_HOST_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_HOST_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_HOST_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_HOST_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_HOST_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_DBG_PRIORITY HW_REGISTER_RW( 0x7e009004 )
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#define SYSAC_DBG_PRIORITY_MASK 0x0000000f
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#define SYSAC_DBG_PRIORITY_WIDTH 4
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#define SYSAC_DBG_PRIORITY_RESET 0000000000
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#define SYSAC_DBG_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_DBG_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_DBG_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_DBG_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_DBG_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_DBG_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_HVSM_PRIORITY HW_REGISTER_RW( 0x7e009008 )
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#define SYSAC_HVSM_PRIORITY_MASK 0x000000ff
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#define SYSAC_HVSM_PRIORITY_WIDTH 8
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#define SYSAC_HVSM_PRIORITY_RESET 0000000000
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_BITS 7:4
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_SET 0x000000f0
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_CLR 0xffffff0f
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_MSB 7
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_LSB 4
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#define SYSAC_HVSM_PRIORITY_P_PRIORITY_RESET 0x0
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_BITS 3:0
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_SET 0x0000000f
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_CLR 0xfffffff0
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_MSB 3
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_LSB 0
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#define SYSAC_HVSM_PRIORITY_N_PRIORITY_RESET 0x0
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#define SYSAC_V3D_PRIORITY HW_REGISTER_RW( 0x7e00900c )
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#define SYSAC_V3D_PRIORITY_MASK 0x0000000f
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#define SYSAC_V3D_PRIORITY_WIDTH 4
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#define SYSAC_V3D_PRIORITY_RESET 0000000000
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#define SYSAC_V3D_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_V3D_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_V3D_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_V3D_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_V3D_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_V3D_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_H264_PRIORITY HW_REGISTER_RW( 0x7e009010 )
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#define SYSAC_H264_PRIORITY_MASK 0x0000000f
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#define SYSAC_H264_PRIORITY_WIDTH 4
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#define SYSAC_H264_PRIORITY_RESET 0000000000
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#define SYSAC_H264_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_H264_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_H264_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_H264_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_H264_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_H264_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_JPEG_PRIORITY HW_REGISTER_RW( 0x7e009014 )
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#define SYSAC_JPEG_PRIORITY_MASK 0x000000ff
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#define SYSAC_JPEG_PRIORITY_WIDTH 8
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#define SYSAC_JPEG_PRIORITY_RESET 0000000000
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_BITS 7:4
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_SET 0x000000f0
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_CLR 0xffffff0f
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_MSB 7
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_LSB 4
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#define SYSAC_JPEG_PRIORITY_P_PRIORITY_RESET 0x0
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_BITS 3:0
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_SET 0x0000000f
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_CLR 0xfffffff0
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_MSB 3
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_LSB 0
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#define SYSAC_JPEG_PRIORITY_N_PRIORITY_RESET 0x0
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#define SYSAC_TRANS_PRIORITY HW_REGISTER_RW( 0x7e009018 )
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#define SYSAC_TRANS_PRIORITY_MASK 0x000000ff
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#define SYSAC_TRANS_PRIORITY_WIDTH 8
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#define SYSAC_TRANS_PRIORITY_RESET 0000000000
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_BITS 7:4
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_SET 0x000000f0
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_CLR 0xffffff0f
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_MSB 7
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_LSB 4
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#define SYSAC_TRANS_PRIORITY_P_PRIORITY_RESET 0x0
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_BITS 3:0
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_SET 0x0000000f
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_CLR 0xfffffff0
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_MSB 3
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_LSB 0
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#define SYSAC_TRANS_PRIORITY_N_PRIORITY_RESET 0x0
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#define SYSAC_ISP_PRIORITY HW_REGISTER_RW( 0x7e00901c )
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#define SYSAC_ISP_PRIORITY_MASK 0x0000000f
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#define SYSAC_ISP_PRIORITY_WIDTH 4
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#define SYSAC_ISP_PRIORITY_RESET 0000000000
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#define SYSAC_ISP_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_ISP_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_ISP_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_ISP_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_ISP_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_ISP_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_USB_PRIORITY HW_REGISTER_RW( 0x7e009020 )
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#define SYSAC_USB_PRIORITY_MASK 0x0000000f
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#define SYSAC_USB_PRIORITY_WIDTH 4
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#define SYSAC_USB_PRIORITY_RESET 0000000000
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#define SYSAC_USB_PRIORITY_PRIORITY_BITS 3:0
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#define SYSAC_USB_PRIORITY_PRIORITY_SET 0x0000000f
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#define SYSAC_USB_PRIORITY_PRIORITY_CLR 0xfffffff0
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#define SYSAC_USB_PRIORITY_PRIORITY_MSB 3
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#define SYSAC_USB_PRIORITY_PRIORITY_LSB 0
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#define SYSAC_USB_PRIORITY_PRIORITY_RESET 0x0
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#define SYSAC_L2_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009040 )
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#define SYSAC_L2_ARBITER_CONTROL_MASK 0x0000ffff
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#define SYSAC_L2_ARBITER_CONTROL_WIDTH 16
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#define SYSAC_L2_ARBITER_CONTROL_RESET 0000000000
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
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#define SYSAC_L2_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_BITS 7:6
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_MSB 7
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_LSB 6
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#define SYSAC_L2_ARBITER_CONTROL_ALGORITHM_RESET 0x0
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_BITS 5:4
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_MSB 5
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_LSB 4
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#define SYSAC_L2_ARBITER_CONTROL_THRESHOLD_RESET 0x0
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_BITS 3:2
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_SET 0x0000000c
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_MSB 3
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_LSB 2
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#define SYSAC_L2_ARBITER_CONTROL_DELAY_RESET 0x0
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_BITS 1:0
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_SET 0x00000003
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_MSB 1
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_LSB 0
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#define SYSAC_L2_ARBITER_CONTROL_LIMIT_RESET 0x0
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#define SYSAC_UC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009044 )
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#define SYSAC_UC_ARBITER_CONTROL_MASK 0x0000ffff
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#define SYSAC_UC_ARBITER_CONTROL_WIDTH 16
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#define SYSAC_UC_ARBITER_CONTROL_RESET 0000000000
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
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#define SYSAC_UC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_MSB 7
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_LSB 6
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#define SYSAC_UC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_MSB 5
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_LSB 4
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#define SYSAC_UC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_BITS 3:2
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_SET 0x0000000c
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_MSB 3
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_LSB 2
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#define SYSAC_UC_ARBITER_CONTROL_DELAY_RESET 0x0
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_BITS 1:0
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_SET 0x00000003
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_MSB 1
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_LSB 0
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#define SYSAC_UC_ARBITER_CONTROL_LIMIT_RESET 0x0
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#define SYSAC_SRC_ARBITER_CONTROL HW_REGISTER_RW( 0x7e009048 )
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#define SYSAC_SRC_ARBITER_CONTROL_MASK 0x0000ffff
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#define SYSAC_SRC_ARBITER_CONTROL_WIDTH 16
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#define SYSAC_SRC_ARBITER_CONTROL_RESET 0000000000
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
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#define SYSAC_SRC_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_BITS 7:6
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_MSB 7
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_LSB 6
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#define SYSAC_SRC_ARBITER_CONTROL_ALGORITHM_RESET 0x0
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_BITS 5:4
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_MSB 5
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_LSB 4
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#define SYSAC_SRC_ARBITER_CONTROL_THRESHOLD_RESET 0x0
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_BITS 3:2
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_SET 0x0000000c
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_MSB 3
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_LSB 2
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#define SYSAC_SRC_ARBITER_CONTROL_DELAY_RESET 0x0
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_BITS 1:0
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_SET 0x00000003
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_MSB 1
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_LSB 0
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#define SYSAC_SRC_ARBITER_CONTROL_LIMIT_RESET 0x0
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#define SYSAC_PERI_ARBITER_CONTROL HW_REGISTER_RW( 0x7e00904c )
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#define SYSAC_PERI_ARBITER_CONTROL_MASK 0x0000ffff
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#define SYSAC_PERI_ARBITER_CONTROL_WIDTH 16
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#define SYSAC_PERI_ARBITER_CONTROL_RESET 0000000000
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_MSB 15
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_LSB 8
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#define SYSAC_PERI_ARBITER_CONTROL_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_BITS 7:6
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_SET 0x000000c0
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_MSB 7
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_LSB 6
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#define SYSAC_PERI_ARBITER_CONTROL_ALGORITHM_RESET 0x0
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_BITS 5:4
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_SET 0x00000030
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_MSB 5
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_LSB 4
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#define SYSAC_PERI_ARBITER_CONTROL_THRESHOLD_RESET 0x0
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_BITS 3:2
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_SET 0x0000000c
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_CLR 0xfffffff3
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_MSB 3
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_LSB 2
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#define SYSAC_PERI_ARBITER_CONTROL_DELAY_RESET 0x0
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_BITS 1:0
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_SET 0x00000003
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_CLR 0xfffffffc
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_MSB 1
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_LSB 0
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#define SYSAC_PERI_ARBITER_CONTROL_LIMIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_UC HW_REGISTER_RW( 0x7e009050 )
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#define SYSAC_DMA_ARBITER_CONTROL_UC_MASK 0x0000ffff
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#define SYSAC_DMA_ARBITER_CONTROL_UC_WIDTH 16
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#define SYSAC_DMA_ARBITER_CONTROL_UC_RESET 0000000000
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_MSB 15
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_LSB 8
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#define SYSAC_DMA_ARBITER_CONTROL_UC_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_BITS 7:6
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_SET 0x000000c0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_MSB 7
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_LSB 6
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#define SYSAC_DMA_ARBITER_CONTROL_UC_ALGORITHM_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_BITS 5:4
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_SET 0x00000030
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_MSB 5
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_LSB 4
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#define SYSAC_DMA_ARBITER_CONTROL_UC_THRESHOLD_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_BITS 3:2
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_SET 0x0000000c
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_CLR 0xfffffff3
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_MSB 3
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_LSB 2
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#define SYSAC_DMA_ARBITER_CONTROL_UC_DELAY_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_BITS 1:0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_SET 0x00000003
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_CLR 0xfffffffc
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_MSB 1
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_LSB 0
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#define SYSAC_DMA_ARBITER_CONTROL_UC_LIMIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_L2 HW_REGISTER_RW( 0x7e009054 )
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#define SYSAC_DMA_ARBITER_CONTROL_L2_MASK 0x0000ffff
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#define SYSAC_DMA_ARBITER_CONTROL_L2_WIDTH 16
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#define SYSAC_DMA_ARBITER_CONTROL_L2_RESET 0000000000
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_BITS 7:6
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_SET 0x000000c0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_MSB 7
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_LSB 6
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#define SYSAC_DMA_ARBITER_CONTROL_L2_ALGORITHM_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_BITS 5:4
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_SET 0x00000030
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_MSB 5
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_LSB 4
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#define SYSAC_DMA_ARBITER_CONTROL_L2_THRESHOLD_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_BITS 3:2
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_SET 0x0000000c
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_CLR 0xfffffff3
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_MSB 3
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_LSB 2
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#define SYSAC_DMA_ARBITER_CONTROL_L2_DELAY_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_BITS 1:0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_SET 0x00000003
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_CLR 0xfffffffc
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_MSB 1
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_LSB 0
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#define SYSAC_DMA_ARBITER_CONTROL_L2_LIMIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_PER HW_REGISTER_RW( 0x7e009058 )
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#define SYSAC_DMA_ARBITER_CONTROL_PER_MASK 0x0000ffff
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#define SYSAC_DMA_ARBITER_CONTROL_PER_WIDTH 16
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#define SYSAC_DMA_ARBITER_CONTROL_PER_RESET 0000000000
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_MSB 15
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_LSB 8
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#define SYSAC_DMA_ARBITER_CONTROL_PER_CHANNEL_INIBIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_BITS 7:6
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_SET 0x000000c0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_MSB 7
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_LSB 6
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#define SYSAC_DMA_ARBITER_CONTROL_PER_ALGORITHM_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_BITS 5:4
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_SET 0x00000030
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_MSB 5
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_LSB 4
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#define SYSAC_DMA_ARBITER_CONTROL_PER_THRESHOLD_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_BITS 3:2
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_SET 0x0000000c
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_CLR 0xfffffff3
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_MSB 3
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_LSB 2
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#define SYSAC_DMA_ARBITER_CONTROL_PER_DELAY_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_BITS 1:0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_SET 0x00000003
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_CLR 0xfffffffc
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_MSB 1
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_LSB 0
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#define SYSAC_DMA_ARBITER_CONTROL_PER_LIMIT_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE HW_REGISTER_RW( 0x7e00905c )
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_MASK 0x0000ffff
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_WIDTH 16
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_RESET 0000000000
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_BITS 15:8
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_SET 0x0000ff00
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_CLR 0xffff00ff
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_MSB 15
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_LSB 8
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_CHANNEL_INIBIT_RESET0x0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_BITS 7:6
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_SET 0x000000c0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_CLR 0xffffff3f
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_MSB 7
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_LSB 6
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_ALGORITHM_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_BITS 5:4
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_SET 0x00000030
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_CLR 0xffffffcf
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_MSB 5
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_LSB 4
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_THRESHOLD_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_BITS 3:2
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_SET 0x0000000c
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_CLR 0xfffffff3
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_MSB 3
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_LSB 2
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_DELAY_RESET 0x0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_BITS 1:0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_SET 0x00000003
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_CLR 0xfffffffc
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_MSB 1
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_LSB 0
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#define SYSAC_DMA_ARBITER_CONTROL_LITE_LIMIT_RESET 0x0
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#define SYSAC_DUMMY_STATUS HW_REGISTER_RW( 0x7e009060 )
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#define SYSAC_DUMMY_STATUS_MASK 0x00000001
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#define SYSAC_DUMMY_STATUS_WIDTH 1
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#define SYSAC_DUMMY_STATUS_RESET 0000000000
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#define SYSAC_DUMMY_STATUS_IDLE_BITS 0:0
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#define SYSAC_DUMMY_STATUS_IDLE_SET 0x00000001
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#define SYSAC_DUMMY_STATUS_IDLE_CLR 0xfffffffe
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#define SYSAC_DUMMY_STATUS_IDLE_MSB 0
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#define SYSAC_DUMMY_STATUS_IDLE_LSB 0
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#define SYSAC_DUMMY_STATUS_IDLE_RESET 0x0
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#define SYSAC_DMA_DREQ_CONTROL HW_REGISTER_RW( 0x7e009064 )
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#define SYSAC_DMA_DREQ_CONTROL_MASK 0x0000000f
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#define SYSAC_DMA_DREQ_CONTROL_WIDTH 4
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#define SYSAC_DMA_DREQ_CONTROL_RESET 0000000000
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_BITS 2:0
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_SET 0x00000007
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_CLR 0xfffffff8
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_MSB 2
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_LSB 0
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#define SYSAC_DMA_DREQ_CONTROL_SMI_DISABLE_RESET 0x0
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_BITS 3:3
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_SET 0x00000008
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_CLR 0xfffffff7
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_MSB 3
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_LSB 3
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#define SYSAC_DMA_DREQ_CONTROL_DMA_DBG_PAUSE_OR_RESET 0x0
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#define SYSAC_V3D_LIMITER HW_REGISTER_RW( 0x7e009068 )
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#define SYSAC_V3D_LIMITER_MASK 0x00000fff
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#define SYSAC_V3D_LIMITER_WIDTH 12
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#define SYSAC_V3D_LIMITER_RESET 0000000000
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#define SYSAC_V3D_LIMITER_ENABLE_BITS 0:0
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#define SYSAC_V3D_LIMITER_ENABLE_SET 0x00000001
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#define SYSAC_V3D_LIMITER_ENABLE_CLR 0xfffffffe
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#define SYSAC_V3D_LIMITER_ENABLE_MSB 0
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#define SYSAC_V3D_LIMITER_ENABLE_LSB 0
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#define SYSAC_V3D_LIMITER_ENABLE_RESET 0x0
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#define SYSAC_V3D_LIMITER_SPARE_BITS 3:1
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#define SYSAC_V3D_LIMITER_SPARE_SET 0x0000000e
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#define SYSAC_V3D_LIMITER_SPARE_CLR 0xfffffff1
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#define SYSAC_V3D_LIMITER_SPARE_MSB 3
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#define SYSAC_V3D_LIMITER_SPARE_LSB 1
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#define SYSAC_V3D_LIMITER_SPARE_RESET 0x0
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_BITS 7:3
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_SET 0x000000f8
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_CLR 0xffffff07
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_MSB 7
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_LSB 3
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#define SYSAC_V3D_LIMITER_MAX_PRIORITY_RESET 0x0
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#define SYSAC_V3D_LIMITER_INCREMENT_BITS 0:0
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#define SYSAC_V3D_LIMITER_INCREMENT_SET 0x00000001
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#define SYSAC_V3D_LIMITER_INCREMENT_CLR 0xfffffffe
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#define SYSAC_V3D_LIMITER_INCREMENT_MSB 0
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#define SYSAC_V3D_LIMITER_INCREMENT_LSB 0
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#define SYSAC_V3D_LIMITER_INCREMENT_RESET 0x0
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#define SYSAC_V3D_LIMITER_HOLDOFF_BITS 0:0
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#define SYSAC_V3D_LIMITER_HOLDOFF_SET 0x00000001
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#define SYSAC_V3D_LIMITER_HOLDOFF_CLR 0xfffffffe
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#define SYSAC_V3D_LIMITER_HOLDOFF_MSB 0
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#define SYSAC_V3D_LIMITER_HOLDOFF_LSB 0
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#define SYSAC_V3D_LIMITER_HOLDOFF_RESET 0x0
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