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rpi-open-firmware/bcm2708_chip/usb.h
kristina 49a15e3a39 Initial commit
2016-05-16 03:01:46 +01:00

2890 lines
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// This file was generated by the create_regs script
#define USB_BASE 0x7e980000
#define USB_APB_ID 0x75736230
#define USB_GOTGCTL HW_REGISTER_RW( 0x7e980000 )
#define USB_GOTGCTL_MASK 0x000f0f03
#define USB_GOTGCTL_WIDTH 20
#define USB_GOTGCTL_B_SES_VLD_BITS 19:19
#define USB_GOTGCTL_B_SES_VLD_SET 0x00080000
#define USB_GOTGCTL_B_SES_VLD_CLR 0xfff7ffff
#define USB_GOTGCTL_B_SES_VLD_MSB 19
#define USB_GOTGCTL_B_SES_VLD_LSB 19
#define USB_GOTGCTL_B_SES_VLD_RESET 0x0
#define USB_GOTGCTL_A_SES_VLD_BITS 18:18
#define USB_GOTGCTL_A_SES_VLD_SET 0x00040000
#define USB_GOTGCTL_A_SES_VLD_CLR 0xfffbffff
#define USB_GOTGCTL_A_SES_VLD_MSB 18
#define USB_GOTGCTL_A_SES_VLD_LSB 18
#define USB_GOTGCTL_A_SES_VLD_RESET 0x0
#define USB_GOTGCTL_DBNC_TIME_BITS 17:17
#define USB_GOTGCTL_DBNC_TIME_SET 0x00020000
#define USB_GOTGCTL_DBNC_TIME_CLR 0xfffdffff
#define USB_GOTGCTL_DBNC_TIME_MSB 17
#define USB_GOTGCTL_DBNC_TIME_LSB 17
#define USB_GOTGCTL_DBNC_TIME_RESET 0x0
#define USB_GOTGCTL_CON_ID_STS_BITS 16:16
#define USB_GOTGCTL_CON_ID_STS_SET 0x00010000
#define USB_GOTGCTL_CON_ID_STS_CLR 0xfffeffff
#define USB_GOTGCTL_CON_ID_STS_MSB 16
#define USB_GOTGCTL_CON_ID_STS_LSB 16
#define USB_GOTGCTL_CON_ID_STS_RESET 0x0
#define USB_GOTGCTL_DEV_HNP_EN_BITS 11:11
#define USB_GOTGCTL_DEV_HNP_EN_SET 0x00000800
#define USB_GOTGCTL_DEV_HNP_EN_CLR 0xfffff7ff
#define USB_GOTGCTL_DEV_HNP_EN_MSB 11
#define USB_GOTGCTL_DEV_HNP_EN_LSB 11
#define USB_GOTGCTL_DEV_HNP_EN_RESET 0x0
#define USB_GOTGCTL_HST_SET_HNP_EN_BITS 10:10
#define USB_GOTGCTL_HST_SET_HNP_EN_SET 0x00000400
#define USB_GOTGCTL_HST_SET_HNP_EN_CLR 0xfffffbff
#define USB_GOTGCTL_HST_SET_HNP_EN_MSB 10
#define USB_GOTGCTL_HST_SET_HNP_EN_LSB 10
#define USB_GOTGCTL_HST_SET_HNP_EN_RESET 0x0
#define USB_GOTGCTL_HNP_REQ_BITS 9:9
#define USB_GOTGCTL_HNP_REQ_SET 0x00000200
#define USB_GOTGCTL_HNP_REQ_CLR 0xfffffdff
#define USB_GOTGCTL_HNP_REQ_MSB 9
#define USB_GOTGCTL_HNP_REQ_LSB 9
#define USB_GOTGCTL_HNP_REQ_RESET 0x0
#define USB_GOTGCTL_HST_NEG_SCS_BITS 8:8
#define USB_GOTGCTL_HST_NEG_SCS_SET 0x00000100
#define USB_GOTGCTL_HST_NEG_SCS_CLR 0xfffffeff
#define USB_GOTGCTL_HST_NEG_SCS_MSB 8
#define USB_GOTGCTL_HST_NEG_SCS_LSB 8
#define USB_GOTGCTL_HST_NEG_SCS_RESET 0x0
#define USB_GOTGCTL_SES_REQ_BITS 1:1
#define USB_GOTGCTL_SES_REQ_SET 0x00000002
#define USB_GOTGCTL_SES_REQ_CLR 0xfffffffd
#define USB_GOTGCTL_SES_REQ_MSB 1
#define USB_GOTGCTL_SES_REQ_LSB 1
#define USB_GOTGCTL_SES_REQ_RESET 0x0
#define USB_GOTGCTL_SES_REQ_SCS_BITS 0:0
#define USB_GOTGCTL_SES_REQ_SCS_SET 0x00000001
#define USB_GOTGCTL_SES_REQ_SCS_CLR 0xfffffffe
#define USB_GOTGCTL_SES_REQ_SCS_MSB 0
#define USB_GOTGCTL_SES_REQ_SCS_LSB 0
#define USB_GOTGCTL_SES_REQ_SCS_RESET 0x0
#define USB_GOTGINT HW_REGISTER_RW( 0x7e980004 )
#define USB_GOTGINT_MASK 0x000e0304
#define USB_GOTGINT_WIDTH 20
#define USB_GOTGINT_DBNCE_DONE_BITS 19:19
#define USB_GOTGINT_DBNCE_DONE_SET 0x00080000
#define USB_GOTGINT_DBNCE_DONE_CLR 0xfff7ffff
#define USB_GOTGINT_DBNCE_DONE_MSB 19
#define USB_GOTGINT_DBNCE_DONE_LSB 19
#define USB_GOTGINT_DBNCE_DONE_RESET 0x0
#define USB_GOTGINT_A_DEV_TOUT_CHG_BITS 18:18
#define USB_GOTGINT_A_DEV_TOUT_CHG_SET 0x00040000
#define USB_GOTGINT_A_DEV_TOUT_CHG_CLR 0xfffbffff
#define USB_GOTGINT_A_DEV_TOUT_CHG_MSB 18
#define USB_GOTGINT_A_DEV_TOUT_CHG_LSB 18
#define USB_GOTGINT_A_DEV_TOUT_CHG_RESET 0x0
#define USB_GOTGINT_HST_NEG_DET_BITS 17:17
#define USB_GOTGINT_HST_NEG_DET_SET 0x00020000
#define USB_GOTGINT_HST_NEG_DET_CLR 0xfffdffff
#define USB_GOTGINT_HST_NEG_DET_MSB 17
#define USB_GOTGINT_HST_NEG_DET_LSB 17
#define USB_GOTGINT_HST_NEG_DET_RESET 0x0
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_BITS 9:9
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_SET 0x00000200
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_CLR 0xfffffdff
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_MSB 9
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_LSB 9
#define USB_GOTGINT_HST_NEG_SUC_STS_CHG_RESET 0x0
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_BITS 8:8
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_SET 0x00000100
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_CLR 0xfffffeff
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_MSB 8
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_LSB 8
#define USB_GOTGINT_SES_REQ_SUC_STS_CHG_RESET 0x0
#define USB_GOTGINT_SES_END_DET_BITS 2:2
#define USB_GOTGINT_SES_END_DET_SET 0x00000004
#define USB_GOTGINT_SES_END_DET_CLR 0xfffffffb
#define USB_GOTGINT_SES_END_DET_MSB 2
#define USB_GOTGINT_SES_END_DET_LSB 2
#define USB_GOTGINT_SES_END_DET_RESET 0x0
#define USB_GAHBCFG HW_REGISTER_RW( 0x7e980008 )
#define USB_GAHBCFG_MASK 0x000001bf
#define USB_GAHBCFG_WIDTH 9
#define USB_GAHBCFG_P_TXF_EMP_LVL_BITS 8:8
#define USB_GAHBCFG_P_TXF_EMP_LVL_SET 0x00000100
#define USB_GAHBCFG_P_TXF_EMP_LVL_CLR 0xfffffeff
#define USB_GAHBCFG_P_TXF_EMP_LVL_MSB 8
#define USB_GAHBCFG_P_TXF_EMP_LVL_LSB 8
#define USB_GAHBCFG_P_TXF_EMP_LVL_RESET 0x0
#define USB_GAHBCFG_NP_TXF_EMP_LVL_BITS 7:7
#define USB_GAHBCFG_NP_TXF_EMP_LVL_SET 0x00000080
#define USB_GAHBCFG_NP_TXF_EMP_LVL_CLR 0xffffff7f
#define USB_GAHBCFG_NP_TXF_EMP_LVL_MSB 7
#define USB_GAHBCFG_NP_TXF_EMP_LVL_LSB 7
#define USB_GAHBCFG_NP_TXF_EMP_LVL_RESET 0x0
#define USB_GAHBCFG_DMA_EN_BITS 5:5
#define USB_GAHBCFG_DMA_EN_SET 0x00000020
#define USB_GAHBCFG_DMA_EN_CLR 0xffffffdf
#define USB_GAHBCFG_DMA_EN_MSB 5
#define USB_GAHBCFG_DMA_EN_LSB 5
#define USB_GAHBCFG_DMA_EN_RESET 0x0
#define USB_GAHBCFG_H_BST_LEN_BITS 4:1
#define USB_GAHBCFG_H_BST_LEN_SET 0x0000001e
#define USB_GAHBCFG_H_BST_LEN_CLR 0xffffffe1
#define USB_GAHBCFG_H_BST_LEN_MSB 4
#define USB_GAHBCFG_H_BST_LEN_LSB 1
#define USB_GAHBCFG_H_BST_LEN_RESET 0x0
#define USB_GAHBCFG_GLBL_INTR_MSK_BITS 0:0
#define USB_GAHBCFG_GLBL_INTR_MSK_SET 0x00000001
#define USB_GAHBCFG_GLBL_INTR_MSK_CLR 0xfffffffe
#define USB_GAHBCFG_GLBL_INTR_MSK_MSB 0
#define USB_GAHBCFG_GLBL_INTR_MSK_LSB 0
#define USB_GAHBCFG_GLBL_INTR_MSK_RESET 0x0
#define USB_GUSBCFG HW_REGISTER_RW( 0x7e98000c )
#define USB_GUSBCFG_MASK 0xe3ffbfff
#define USB_GUSBCFG_WIDTH 32
#define USB_GUSBCFG_CORRUPT_TX_BITS 31:31
#define USB_GUSBCFG_CORRUPT_TX_SET 0x80000000
#define USB_GUSBCFG_CORRUPT_TX_CLR 0x7fffffff
#define USB_GUSBCFG_CORRUPT_TX_MSB 31
#define USB_GUSBCFG_CORRUPT_TX_LSB 31
#define USB_GUSBCFG_CORRUPT_TX_RESET 0x0
#define USB_GUSBCFG_FORCE_DEV_MODE_BITS 30:30
#define USB_GUSBCFG_FORCE_DEV_MODE_SET 0x40000000
#define USB_GUSBCFG_FORCE_DEV_MODE_CLR 0xbfffffff
#define USB_GUSBCFG_FORCE_DEV_MODE_MSB 30
#define USB_GUSBCFG_FORCE_DEV_MODE_LSB 30
#define USB_GUSBCFG_FORCE_DEV_MODE_RESET 0x0
#define USB_GUSBCFG_FORCE_HST_MODE_BITS 29:29
#define USB_GUSBCFG_FORCE_HST_MODE_SET 0x20000000
#define USB_GUSBCFG_FORCE_HST_MODE_CLR 0xdfffffff
#define USB_GUSBCFG_FORCE_HST_MODE_MSB 29
#define USB_GUSBCFG_FORCE_HST_MODE_LSB 29
#define USB_GUSBCFG_FORCE_HST_MODE_RESET 0x0
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_BITS 25:25
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_SET 0x02000000
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_CLR 0xfdffffff
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_MSB 25
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_LSB 25
#define USB_GUSBCFG_ULPI_IF_PROT_DIS_RESET 0x0
#define USB_GUSBCFG_IND_PASS_THRU_BITS 24:24
#define USB_GUSBCFG_IND_PASS_THRU_SET 0x01000000
#define USB_GUSBCFG_IND_PASS_THRU_CLR 0xfeffffff
#define USB_GUSBCFG_IND_PASS_THRU_MSB 24
#define USB_GUSBCFG_IND_PASS_THRU_LSB 24
#define USB_GUSBCFG_IND_PASS_THRU_RESET 0x0
#define USB_GUSBCFG_IND_COMP_BITS 23:23
#define USB_GUSBCFG_IND_COMP_SET 0x00800000
#define USB_GUSBCFG_IND_COMP_CLR 0xff7fffff
#define USB_GUSBCFG_IND_COMP_MSB 23
#define USB_GUSBCFG_IND_COMP_LSB 23
#define USB_GUSBCFG_IND_COMP_RESET 0x0
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_BITS 22:22
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_SET 0x00400000
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_CLR 0xffbfffff
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_MSB 22
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_LSB 22
#define USB_GUSBCFG_TERM_SEL_DL_PULSE_RESET 0x0
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_BITS 21:21
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_SET 0x00200000
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_CLR 0xffdfffff
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_MSB 21
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_LSB 21
#define USB_GUSBCFG_ULPI_EXT_VBUS_IND_RESET 0x0
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_BITS 20:20
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_SET 0x00100000
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_CLR 0xffefffff
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_MSB 20
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_LSB 20
#define USB_GUSBCFG_ULPI_EXT_VBUS_DRV_RESET 0x0
#define USB_GUSBCFG_ULPI_CLK_SUS_M_BITS 19:19
#define USB_GUSBCFG_ULPI_CLK_SUS_M_SET 0x00080000
#define USB_GUSBCFG_ULPI_CLK_SUS_M_CLR 0xfff7ffff
#define USB_GUSBCFG_ULPI_CLK_SUS_M_MSB 19
#define USB_GUSBCFG_ULPI_CLK_SUS_M_LSB 19
#define USB_GUSBCFG_ULPI_CLK_SUS_M_RESET 0x0
#define USB_GUSBCFG_ULPI_AUTO_RES_BITS 18:18
#define USB_GUSBCFG_ULPI_AUTO_RES_SET 0x00040000
#define USB_GUSBCFG_ULPI_AUTO_RES_CLR 0xfffbffff
#define USB_GUSBCFG_ULPI_AUTO_RES_MSB 18
#define USB_GUSBCFG_ULPI_AUTO_RES_LSB 18
#define USB_GUSBCFG_ULPI_AUTO_RES_RESET 0x0
#define USB_GUSBCFG_ULPI_FS_LS_BITS 17:17
#define USB_GUSBCFG_ULPI_FS_LS_SET 0x00020000
#define USB_GUSBCFG_ULPI_FS_LS_CLR 0xfffdffff
#define USB_GUSBCFG_ULPI_FS_LS_MSB 17
#define USB_GUSBCFG_ULPI_FS_LS_LSB 17
#define USB_GUSBCFG_ULPI_FS_LS_RESET 0x0
#define USB_GUSBCFG_OTG_I2C_SEL_BITS 16:16
#define USB_GUSBCFG_OTG_I2C_SEL_SET 0x00010000
#define USB_GUSBCFG_OTG_I2C_SEL_CLR 0xfffeffff
#define USB_GUSBCFG_OTG_I2C_SEL_MSB 16
#define USB_GUSBCFG_OTG_I2C_SEL_LSB 16
#define USB_GUSBCFG_OTG_I2C_SEL_RESET 0x0
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_BITS 15:15
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_SET 0x00008000
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_CLR 0xffff7fff
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_MSB 15
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_LSB 15
#define USB_GUSBCFG_PHY_LPWR_CLK_SEL_RESET 0x0
#define USB_GUSBCFG_USB_TRD_TIM_BITS 13:10
#define USB_GUSBCFG_USB_TRD_TIM_SET 0x00003c00
#define USB_GUSBCFG_USB_TRD_TIM_CLR 0xffffc3ff
#define USB_GUSBCFG_USB_TRD_TIM_MSB 13
#define USB_GUSBCFG_USB_TRD_TIM_LSB 10
#define USB_GUSBCFG_USB_TRD_TIM_RESET 0x0
#define USB_GUSBCFG_HNP_CAP_BITS 9:9
#define USB_GUSBCFG_HNP_CAP_SET 0x00000200
#define USB_GUSBCFG_HNP_CAP_CLR 0xfffffdff
#define USB_GUSBCFG_HNP_CAP_MSB 9
#define USB_GUSBCFG_HNP_CAP_LSB 9
#define USB_GUSBCFG_HNP_CAP_RESET 0x0
#define USB_GUSBCFG_SRP_CAP_BITS 8:8
#define USB_GUSBCFG_SRP_CAP_SET 0x00000100
#define USB_GUSBCFG_SRP_CAP_CLR 0xfffffeff
#define USB_GUSBCFG_SRP_CAP_MSB 8
#define USB_GUSBCFG_SRP_CAP_LSB 8
#define USB_GUSBCFG_SRP_CAP_RESET 0x0
#define USB_GUSBCFG_DDR_SEL_BITS 7:7
#define USB_GUSBCFG_DDR_SEL_SET 0x00000080
#define USB_GUSBCFG_DDR_SEL_CLR 0xffffff7f
#define USB_GUSBCFG_DDR_SEL_MSB 7
#define USB_GUSBCFG_DDR_SEL_LSB 7
#define USB_GUSBCFG_DDR_SEL_RESET 0x0
#define USB_GUSBCFG_PHY_SEL_BITS 6:6
#define USB_GUSBCFG_PHY_SEL_SET 0x00000040
#define USB_GUSBCFG_PHY_SEL_CLR 0xffffffbf
#define USB_GUSBCFG_PHY_SEL_MSB 6
#define USB_GUSBCFG_PHY_SEL_LSB 6
#define USB_GUSBCFG_PHY_SEL_RESET 0x0
#define USB_GUSBCFG_FS_INTF_BITS 5:5
#define USB_GUSBCFG_FS_INTF_SET 0x00000020
#define USB_GUSBCFG_FS_INTF_CLR 0xffffffdf
#define USB_GUSBCFG_FS_INTF_MSB 5
#define USB_GUSBCFG_FS_INTF_LSB 5
#define USB_GUSBCFG_FS_INTF_RESET 0x0
#define USB_GUSBCFG_ULPI_UTMI_SEL_BITS 4:4
#define USB_GUSBCFG_ULPI_UTMI_SEL_SET 0x00000010
#define USB_GUSBCFG_ULPI_UTMI_SEL_CLR 0xffffffef
#define USB_GUSBCFG_ULPI_UTMI_SEL_MSB 4
#define USB_GUSBCFG_ULPI_UTMI_SEL_LSB 4
#define USB_GUSBCFG_ULPI_UTMI_SEL_RESET 0x0
#define USB_GUSBCFG_PHY_IF_BITS 3:3
#define USB_GUSBCFG_PHY_IF_SET 0x00000008
#define USB_GUSBCFG_PHY_IF_CLR 0xfffffff7
#define USB_GUSBCFG_PHY_IF_MSB 3
#define USB_GUSBCFG_PHY_IF_LSB 3
#define USB_GUSBCFG_PHY_IF_RESET 0x0
#define USB_GUSBCFG_TOUT_CAL_BITS 2:0
#define USB_GUSBCFG_TOUT_CAL_SET 0x00000007
#define USB_GUSBCFG_TOUT_CAL_CLR 0xfffffff8
#define USB_GUSBCFG_TOUT_CAL_MSB 2
#define USB_GUSBCFG_TOUT_CAL_LSB 0
#define USB_GUSBCFG_TOUT_CAL_RESET 0x0
#define USB_GRSTCTL HW_REGISTER_RW( 0x7e980010 )
#define USB_GRSTCTL_MASK 0xc00007ff
#define USB_GRSTCTL_WIDTH 32
#define USB_GRSTCTL_AHB_IDLE_BITS 31:31
#define USB_GRSTCTL_AHB_IDLE_SET 0x80000000
#define USB_GRSTCTL_AHB_IDLE_CLR 0x7fffffff
#define USB_GRSTCTL_AHB_IDLE_MSB 31
#define USB_GRSTCTL_AHB_IDLE_LSB 31
#define USB_GRSTCTL_AHB_IDLE_RESET 0x0
#define USB_GRSTCTL_DMA_REQ_BITS 30:30
#define USB_GRSTCTL_DMA_REQ_SET 0x40000000
#define USB_GRSTCTL_DMA_REQ_CLR 0xbfffffff
#define USB_GRSTCTL_DMA_REQ_MSB 30
#define USB_GRSTCTL_DMA_REQ_LSB 30
#define USB_GRSTCTL_DMA_REQ_RESET 0x0
#define USB_GRSTCTL_TXF_NUM_BITS 10:6
#define USB_GRSTCTL_TXF_NUM_SET 0x000007c0
#define USB_GRSTCTL_TXF_NUM_CLR 0xfffff83f
#define USB_GRSTCTL_TXF_NUM_MSB 10
#define USB_GRSTCTL_TXF_NUM_LSB 6
#define USB_GRSTCTL_TXF_NUM_RESET 0x0
#define USB_GRSTCTL_TXF_FLSH_BITS 5:5
#define USB_GRSTCTL_TXF_FLSH_SET 0x00000020
#define USB_GRSTCTL_TXF_FLSH_CLR 0xffffffdf
#define USB_GRSTCTL_TXF_FLSH_MSB 5
#define USB_GRSTCTL_TXF_FLSH_LSB 5
#define USB_GRSTCTL_TXF_FLSH_RESET 0x0
#define USB_GRSTCTL_RXF_FLSH_BITS 4:4
#define USB_GRSTCTL_RXF_FLSH_SET 0x00000010
#define USB_GRSTCTL_RXF_FLSH_CLR 0xffffffef
#define USB_GRSTCTL_RXF_FLSH_MSB 4
#define USB_GRSTCTL_RXF_FLSH_LSB 4
#define USB_GRSTCTL_RXF_FLSH_RESET 0x0
#define USB_GRSTCTL_INT_TKN_Q_FLSH_BITS 3:3
#define USB_GRSTCTL_INT_TKN_Q_FLSH_SET 0x00000008
#define USB_GRSTCTL_INT_TKN_Q_FLSH_CLR 0xfffffff7
#define USB_GRSTCTL_INT_TKN_Q_FLSH_MSB 3
#define USB_GRSTCTL_INT_TKN_Q_FLSH_LSB 3
#define USB_GRSTCTL_INT_TKN_Q_FLSH_RESET 0x0
#define USB_GRSTCTL_FRM_CNTR_RST_BITS 2:2
#define USB_GRSTCTL_FRM_CNTR_RST_SET 0x00000004
#define USB_GRSTCTL_FRM_CNTR_RST_CLR 0xfffffffb
#define USB_GRSTCTL_FRM_CNTR_RST_MSB 2
#define USB_GRSTCTL_FRM_CNTR_RST_LSB 2
#define USB_GRSTCTL_FRM_CNTR_RST_RESET 0x0
#define USB_GRSTCTL_H_SFT_RST_BITS 1:1
#define USB_GRSTCTL_H_SFT_RST_SET 0x00000002
#define USB_GRSTCTL_H_SFT_RST_CLR 0xfffffffd
#define USB_GRSTCTL_H_SFT_RST_MSB 1
#define USB_GRSTCTL_H_SFT_RST_LSB 1
#define USB_GRSTCTL_H_SFT_RST_RESET 0x0
#define USB_GRSTCTL_C_SFT_RST_BITS 0:0
#define USB_GRSTCTL_C_SFT_RST_SET 0x00000001
#define USB_GRSTCTL_C_SFT_RST_CLR 0xfffffffe
#define USB_GRSTCTL_C_SFT_RST_MSB 0
#define USB_GRSTCTL_C_SFT_RST_LSB 0
#define USB_GRSTCTL_C_SFT_RST_RESET 0x0
#define USB_GINTSTS HW_REGISTER_RW( 0x7e980014 )
#define USB_GINTSTS_MASK 0xffffffff
#define USB_GINTSTS_WIDTH 32
#define USB_GINTMSK HW_REGISTER_RW( 0x7e980018 )
#define USB_GINTMSK_MASK 0xf77effff
#define USB_GINTMSK_WIDTH 32
#define USB_GINTMSK_WK_UP_INT_BITS 31:31
#define USB_GINTMSK_WK_UP_INT_SET 0x80000000
#define USB_GINTMSK_WK_UP_INT_CLR 0x7fffffff
#define USB_GINTMSK_WK_UP_INT_MSB 31
#define USB_GINTMSK_WK_UP_INT_LSB 31
#define USB_GINTMSK_WK_UP_INT_RESET 0x0
#define USB_GINTMSK_SESS_REQ_INT_BITS 30:30
#define USB_GINTMSK_SESS_REQ_INT_SET 0x40000000
#define USB_GINTMSK_SESS_REQ_INT_CLR 0xbfffffff
#define USB_GINTMSK_SESS_REQ_INT_MSB 30
#define USB_GINTMSK_SESS_REQ_INT_LSB 30
#define USB_GINTMSK_SESS_REQ_INT_RESET 0x0
#define USB_GINTMSK_DISCONN_INT_BITS 29:29
#define USB_GINTMSK_DISCONN_INT_SET 0x20000000
#define USB_GINTMSK_DISCONN_INT_CLR 0xdfffffff
#define USB_GINTMSK_DISCONN_INT_MSB 29
#define USB_GINTMSK_DISCONN_INT_LSB 29
#define USB_GINTMSK_DISCONN_INT_RESET 0x0
#define USB_GINTMSK_CON_ID_STS_CHNG_BITS 28:28
#define USB_GINTMSK_CON_ID_STS_CHNG_SET 0x10000000
#define USB_GINTMSK_CON_ID_STS_CHNG_CLR 0xefffffff
#define USB_GINTMSK_CON_ID_STS_CHNG_MSB 28
#define USB_GINTMSK_CON_ID_STS_CHNG_LSB 28
#define USB_GINTMSK_CON_ID_STS_CHNG_RESET 0x0
#define USB_GINTMSK_P_TXF_EMP_BITS 26:26
#define USB_GINTMSK_P_TXF_EMP_SET 0x04000000
#define USB_GINTMSK_P_TXF_EMP_CLR 0xfbffffff
#define USB_GINTMSK_P_TXF_EMP_MSB 26
#define USB_GINTMSK_P_TXF_EMP_LSB 26
#define USB_GINTMSK_P_TXF_EMP_RESET 0x0
#define USB_GINTMSK_HCH_INT_BITS 25:25
#define USB_GINTMSK_HCH_INT_SET 0x02000000
#define USB_GINTMSK_HCH_INT_CLR 0xfdffffff
#define USB_GINTMSK_HCH_INT_MSB 25
#define USB_GINTMSK_HCH_INT_LSB 25
#define USB_GINTMSK_HCH_INT_RESET 0x0
#define USB_GINTMSK_PRT_INT_BITS 24:24
#define USB_GINTMSK_PRT_INT_SET 0x01000000
#define USB_GINTMSK_PRT_INT_CLR 0xfeffffff
#define USB_GINTMSK_PRT_INT_MSB 24
#define USB_GINTMSK_PRT_INT_LSB 24
#define USB_GINTMSK_PRT_INT_RESET 0x0
#define USB_GINTMSK_FET_SUSP_BITS 22:22
#define USB_GINTMSK_FET_SUSP_SET 0x00400000
#define USB_GINTMSK_FET_SUSP_CLR 0xffbfffff
#define USB_GINTMSK_FET_SUSP_MSB 22
#define USB_GINTMSK_FET_SUSP_LSB 22
#define USB_GINTMSK_FET_SUSP_RESET 0x0
#define USB_GINTMSK_INCOMPL_P_BITS 21:21
#define USB_GINTMSK_INCOMPL_P_SET 0x00200000
#define USB_GINTMSK_INCOMPL_P_CLR 0xffdfffff
#define USB_GINTMSK_INCOMPL_P_MSB 21
#define USB_GINTMSK_INCOMPL_P_LSB 21
#define USB_GINTMSK_INCOMPL_P_RESET 0x0
#define USB_GINTMSK_INCOMPL_ISO_OUT_BITS 21:21
#define USB_GINTMSK_INCOMPL_ISO_OUT_SET 0x00200000
#define USB_GINTMSK_INCOMPL_ISO_OUT_CLR 0xffdfffff
#define USB_GINTMSK_INCOMPL_ISO_OUT_MSB 21
#define USB_GINTMSK_INCOMPL_ISO_OUT_LSB 21
#define USB_GINTMSK_INCOMPL_ISO_OUT_RESET 0x0
#define USB_GINTMSK_INCOMPL_ISO_IN_BITS 20:20
#define USB_GINTMSK_INCOMPL_ISO_IN_SET 0x00100000
#define USB_GINTMSK_INCOMPL_ISO_IN_CLR 0xffefffff
#define USB_GINTMSK_INCOMPL_ISO_IN_MSB 20
#define USB_GINTMSK_INCOMPL_ISO_IN_LSB 20
#define USB_GINTMSK_INCOMPL_ISO_IN_RESET 0x0
#define USB_GINTMSK_OEP_INT_BITS 19:19
#define USB_GINTMSK_OEP_INT_SET 0x00080000
#define USB_GINTMSK_OEP_INT_CLR 0xfff7ffff
#define USB_GINTMSK_OEP_INT_MSB 19
#define USB_GINTMSK_OEP_INT_LSB 19
#define USB_GINTMSK_OEP_INT_RESET 0x0
#define USB_GINTMSK_IEP_INT_BITS 18:18
#define USB_GINTMSK_IEP_INT_SET 0x00040000
#define USB_GINTMSK_IEP_INT_CLR 0xfffbffff
#define USB_GINTMSK_IEP_INT_MSB 18
#define USB_GINTMSK_IEP_INT_LSB 18
#define USB_GINTMSK_IEP_INT_RESET 0x0
#define USB_GINTMSK_EP_MIS_BITS 17:17
#define USB_GINTMSK_EP_MIS_SET 0x00020000
#define USB_GINTMSK_EP_MIS_CLR 0xfffdffff
#define USB_GINTMSK_EP_MIS_MSB 17
#define USB_GINTMSK_EP_MIS_LSB 17
#define USB_GINTMSK_EP_MIS_RESET 0x0
#define USB_GINTMSK_EOPF_BITS 15:15
#define USB_GINTMSK_EOPF_SET 0x00008000
#define USB_GINTMSK_EOPF_CLR 0xffff7fff
#define USB_GINTMSK_EOPF_MSB 15
#define USB_GINTMSK_EOPF_LSB 15
#define USB_GINTMSK_EOPF_RESET 0x0
#define USB_GINTMSK_ISO_OUT_DROP_BITS 14:14
#define USB_GINTMSK_ISO_OUT_DROP_SET 0x00004000
#define USB_GINTMSK_ISO_OUT_DROP_CLR 0xffffbfff
#define USB_GINTMSK_ISO_OUT_DROP_MSB 14
#define USB_GINTMSK_ISO_OUT_DROP_LSB 14
#define USB_GINTMSK_ISO_OUT_DROP_RESET 0x0
#define USB_GINTMSK_ENUM_DONE_BITS 13:13
#define USB_GINTMSK_ENUM_DONE_SET 0x00002000
#define USB_GINTMSK_ENUM_DONE_CLR 0xffffdfff
#define USB_GINTMSK_ENUM_DONE_MSB 13
#define USB_GINTMSK_ENUM_DONE_LSB 13
#define USB_GINTMSK_ENUM_DONE_RESET 0x0
#define USB_GINTMSK_USB_RST_BITS 12:12
#define USB_GINTMSK_USB_RST_SET 0x00001000
#define USB_GINTMSK_USB_RST_CLR 0xffffefff
#define USB_GINTMSK_USB_RST_MSB 12
#define USB_GINTMSK_USB_RST_LSB 12
#define USB_GINTMSK_USB_RST_RESET 0x0
#define USB_GINTMSK_USB_SUSP_BITS 11:11
#define USB_GINTMSK_USB_SUSP_SET 0x00000800
#define USB_GINTMSK_USB_SUSP_CLR 0xfffff7ff
#define USB_GINTMSK_USB_SUSP_MSB 11
#define USB_GINTMSK_USB_SUSP_LSB 11
#define USB_GINTMSK_USB_SUSP_RESET 0x0
#define USB_GINTMSK_ERLY_SUSP_BITS 10:10
#define USB_GINTMSK_ERLY_SUSP_SET 0x00000400
#define USB_GINTMSK_ERLY_SUSP_CLR 0xfffffbff
#define USB_GINTMSK_ERLY_SUSP_MSB 10
#define USB_GINTMSK_ERLY_SUSP_LSB 10
#define USB_GINTMSK_ERLY_SUSP_RESET 0x0
#define USB_GINTMSK_I2C_INT_BITS 9:9
#define USB_GINTMSK_I2C_INT_SET 0x00000200
#define USB_GINTMSK_I2C_INT_CLR 0xfffffdff
#define USB_GINTMSK_I2C_INT_MSB 9
#define USB_GINTMSK_I2C_INT_LSB 9
#define USB_GINTMSK_I2C_INT_RESET 0x0
#define USB_GINTMSK_ULPI_CK_INT_BITS 8:8
#define USB_GINTMSK_ULPI_CK_INT_SET 0x00000100
#define USB_GINTMSK_ULPI_CK_INT_CLR 0xfffffeff
#define USB_GINTMSK_ULPI_CK_INT_MSB 8
#define USB_GINTMSK_ULPI_CK_INT_LSB 8
#define USB_GINTMSK_ULPI_CK_INT_RESET 0x0
#define USB_GINTMSK_GOUT_NAK_EFF_BITS 7:7
#define USB_GINTMSK_GOUT_NAK_EFF_SET 0x00000080
#define USB_GINTMSK_GOUT_NAK_EFF_CLR 0xffffff7f
#define USB_GINTMSK_GOUT_NAK_EFF_MSB 7
#define USB_GINTMSK_GOUT_NAK_EFF_LSB 7
#define USB_GINTMSK_GOUT_NAK_EFF_RESET 0x0
#define USB_GINTMSK_GIN_N_NAK_EFF_BITS 6:6
#define USB_GINTMSK_GIN_N_NAK_EFF_SET 0x00000040
#define USB_GINTMSK_GIN_N_NAK_EFF_CLR 0xffffffbf
#define USB_GINTMSK_GIN_N_NAK_EFF_MSB 6
#define USB_GINTMSK_GIN_N_NAK_EFF_LSB 6
#define USB_GINTMSK_GIN_N_NAK_EFF_RESET 0x0
#define USB_GINTMSK_NP_TXF_EMP_BITS 5:5
#define USB_GINTMSK_NP_TXF_EMP_SET 0x00000020
#define USB_GINTMSK_NP_TXF_EMP_CLR 0xffffffdf
#define USB_GINTMSK_NP_TXF_EMP_MSB 5
#define USB_GINTMSK_NP_TXF_EMP_LSB 5
#define USB_GINTMSK_NP_TXF_EMP_RESET 0x0
#define USB_GINTMSK_RXF_LVL_BITS 4:4
#define USB_GINTMSK_RXF_LVL_SET 0x00000010
#define USB_GINTMSK_RXF_LVL_CLR 0xffffffef
#define USB_GINTMSK_RXF_LVL_MSB 4
#define USB_GINTMSK_RXF_LVL_LSB 4
#define USB_GINTMSK_RXF_LVL_RESET 0x0
#define USB_GINTMSK_SOF_BITS 3:3
#define USB_GINTMSK_SOF_SET 0x00000008
#define USB_GINTMSK_SOF_CLR 0xfffffff7
#define USB_GINTMSK_SOF_MSB 3
#define USB_GINTMSK_SOF_LSB 3
#define USB_GINTMSK_SOF_RESET 0x0
#define USB_GINTMSK_OTG_INT_BITS 2:2
#define USB_GINTMSK_OTG_INT_SET 0x00000004
#define USB_GINTMSK_OTG_INT_CLR 0xfffffffb
#define USB_GINTMSK_OTG_INT_MSB 2
#define USB_GINTMSK_OTG_INT_LSB 2
#define USB_GINTMSK_OTG_INT_RESET 0x0
#define USB_GINTMSK_MODE_MIS_BITS 1:1
#define USB_GINTMSK_MODE_MIS_SET 0x00000002
#define USB_GINTMSK_MODE_MIS_CLR 0xfffffffd
#define USB_GINTMSK_MODE_MIS_MSB 1
#define USB_GINTMSK_MODE_MIS_LSB 1
#define USB_GINTMSK_MODE_MIS_RESET 0x0
#define USB_GINTMSK_CUR_MOD_BITS 0:0
#define USB_GINTMSK_CUR_MOD_SET 0x00000001
#define USB_GINTMSK_CUR_MOD_CLR 0xfffffffe
#define USB_GINTMSK_CUR_MOD_MSB 0
#define USB_GINTMSK_CUR_MOD_LSB 0
#define USB_GINTMSK_CUR_MOD_RESET 0x0
#define USB_GRXSTSR HW_REGISTER_RW( 0x7e98001c )
#define USB_GRXSTSR_MASK 0xffffffff
#define USB_GRXSTSR_WIDTH 32
#define USB_GRXSTSP HW_REGISTER_RW( 0x7e980020 )
#define USB_GRXSTSP_MASK 0x01ffffff
#define USB_GRXSTSP_WIDTH 25
#define USB_GRXSTSP_HST_PKT_STS_BITS 20:17
#define USB_GRXSTSP_HST_PKT_STS_SET 0x001e0000
#define USB_GRXSTSP_HST_PKT_STS_CLR 0xffe1ffff
#define USB_GRXSTSP_HST_PKT_STS_MSB 20
#define USB_GRXSTSP_HST_PKT_STS_LSB 17
#define USB_GRXSTSP_HST_PKT_STS_RESET 0x0
#define USB_GRXSTSP_HST_DPID_BITS 16:15
#define USB_GRXSTSP_HST_DPID_SET 0x00018000
#define USB_GRXSTSP_HST_DPID_CLR 0xfffe7fff
#define USB_GRXSTSP_HST_DPID_MSB 16
#define USB_GRXSTSP_HST_DPID_LSB 15
#define USB_GRXSTSP_HST_DPID_RESET 0x0
#define USB_GRXSTSP_HST_BCNT_BITS 14:4
#define USB_GRXSTSP_HST_BCNT_SET 0x00007ff0
#define USB_GRXSTSP_HST_BCNT_CLR 0xffff800f
#define USB_GRXSTSP_HST_BCNT_MSB 14
#define USB_GRXSTSP_HST_BCNT_LSB 4
#define USB_GRXSTSP_HST_BCNT_RESET 0x0
#define USB_GRXSTSP_HST_CH_NUM_BITS 3:0
#define USB_GRXSTSP_HST_CH_NUM_SET 0x0000000f
#define USB_GRXSTSP_HST_CH_NUM_CLR 0xfffffff0
#define USB_GRXSTSP_HST_CH_NUM_MSB 3
#define USB_GRXSTSP_HST_CH_NUM_LSB 0
#define USB_GRXSTSP_HST_CH_NUM_RESET 0x0
#define USB_GRXSTSP_DEV_FN_BITS 24:21
#define USB_GRXSTSP_DEV_FN_SET 0x01e00000
#define USB_GRXSTSP_DEV_FN_CLR 0xfe1fffff
#define USB_GRXSTSP_DEV_FN_MSB 24
#define USB_GRXSTSP_DEV_FN_LSB 21
#define USB_GRXSTSP_DEV_FN_RESET 0x0
#define USB_GRXSTSP_DEV_PKT_STS_BITS 20:17
#define USB_GRXSTSP_DEV_PKT_STS_SET 0x001e0000
#define USB_GRXSTSP_DEV_PKT_STS_CLR 0xffe1ffff
#define USB_GRXSTSP_DEV_PKT_STS_MSB 20
#define USB_GRXSTSP_DEV_PKT_STS_LSB 17
#define USB_GRXSTSP_DEV_PKT_STS_RESET 0x0
#define USB_GRXSTSP_DEV_DPID_BITS 16:15
#define USB_GRXSTSP_DEV_DPID_SET 0x00018000
#define USB_GRXSTSP_DEV_DPID_CLR 0xfffe7fff
#define USB_GRXSTSP_DEV_DPID_MSB 16
#define USB_GRXSTSP_DEV_DPID_LSB 15
#define USB_GRXSTSP_DEV_DPID_RESET 0x0
#define USB_GRXSTSP_DEV_BCNT_BITS 14:4
#define USB_GRXSTSP_DEV_BCNT_SET 0x00007ff0
#define USB_GRXSTSP_DEV_BCNT_CLR 0xffff800f
#define USB_GRXSTSP_DEV_BCNT_MSB 14
#define USB_GRXSTSP_DEV_BCNT_LSB 4
#define USB_GRXSTSP_DEV_BCNT_RESET 0x0
#define USB_GRXSTSP_DEV_EP_NUM_BITS 3:0
#define USB_GRXSTSP_DEV_EP_NUM_SET 0x0000000f
#define USB_GRXSTSP_DEV_EP_NUM_CLR 0xfffffff0
#define USB_GRXSTSP_DEV_EP_NUM_MSB 3
#define USB_GRXSTSP_DEV_EP_NUM_LSB 0
#define USB_GRXSTSP_DEV_EP_NUM_RESET 0x0
#define USB_GRXFSIZ HW_REGISTER_RW( 0x7e980024 )
#define USB_GRXFSIZ_MASK 0x0000ffff
#define USB_GRXFSIZ_WIDTH 16
#define USB_GRXFSIZ_GRXF_DEP_BITS 15:0
#define USB_GRXFSIZ_GRXF_DEP_SET 0x0000ffff
#define USB_GRXFSIZ_GRXF_DEP_CLR 0xffff0000
#define USB_GRXFSIZ_GRXF_DEP_MSB 15
#define USB_GRXFSIZ_GRXF_DEP_LSB 0
#define USB_GRXFSIZ_GRXF_DEP_RESET 0x0
#define USB_GNPTXFSIZ HW_REGISTER_RW( 0x7e980028 )
#define USB_GNPTXFSIZ_MASK 0xffffffff
#define USB_GNPTXFSIZ_WIDTH 32
#define USB_GNPTXFSIZ_NP_TXF_DEP_BITS 31:16
#define USB_GNPTXFSIZ_NP_TXF_DEP_SET 0xffff0000
#define USB_GNPTXFSIZ_NP_TXF_DEP_CLR 0x0000ffff
#define USB_GNPTXFSIZ_NP_TXF_DEP_MSB 31
#define USB_GNPTXFSIZ_NP_TXF_DEP_LSB 16
#define USB_GNPTXFSIZ_NP_TXF_DEP_RESET 0x0
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_BITS 15:0
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_SET 0x0000ffff
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_CLR 0xffff0000
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_MSB 15
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_LSB 0
#define USB_GNPTXFSIZ_NP_TXF_ST_ADDR_RESET 0x0
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_BITS 31:16
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_SET 0xffff0000
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_CLR 0x0000ffff
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_MSB 31
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_LSB 16
#define USB_GNPTXFSIZ_IN_EP_TXF0_DEP_RESET 0x0
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_BITS 15:0
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_SET 0x0000ffff
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_CLR 0xffff0000
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_MSB 15
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_LSB 0
#define USB_GNPTXFSIZ_IN_EP_TXF0_ST_ADDR_RESET 0x0
#define USB_GNPTXSTS HW_REGISTER_RW( 0x7e98002c )
#define USB_GNPTXSTS_MASK 0x7fffffff
#define USB_GNPTXSTS_WIDTH 31
#define USB_GNPTXSTS_TX_Q_TOP_BITS 30:24
#define USB_GNPTXSTS_TX_Q_TOP_SET 0x7f000000
#define USB_GNPTXSTS_TX_Q_TOP_CLR 0x80ffffff
#define USB_GNPTXSTS_TX_Q_TOP_MSB 30
#define USB_GNPTXSTS_TX_Q_TOP_LSB 24
#define USB_GNPTXSTS_TX_Q_TOP_RESET 0x0
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_BITS 23:16
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_SET 0x00ff0000
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_CLR 0xff00ffff
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_MSB 23
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_LSB 16
#define USB_GNPTXSTS_TX_Q_SPC_AVAIL_RESET 0x0
#define USB_GNPTXSTS_TXF_SPC_AVAIL_BITS 15:0
#define USB_GNPTXSTS_TXF_SPC_AVAIL_SET 0x0000ffff
#define USB_GNPTXSTS_TXF_SPC_AVAIL_CLR 0xffff0000
#define USB_GNPTXSTS_TXF_SPC_AVAIL_MSB 15
#define USB_GNPTXSTS_TXF_SPC_AVAIL_LSB 0
#define USB_GNPTXSTS_TXF_SPC_AVAIL_RESET 0x0
#define USB_GI2CCTL HW_REGISTER_RW( 0x7e980030 )
#define USB_GI2CCTL_MASK 0xdfffffff
#define USB_GI2CCTL_WIDTH 32
#define USB_GI2CCTL_BSY_DNE_BITS 31:31
#define USB_GI2CCTL_BSY_DNE_SET 0x80000000
#define USB_GI2CCTL_BSY_DNE_CLR 0x7fffffff
#define USB_GI2CCTL_BSY_DNE_MSB 31
#define USB_GI2CCTL_BSY_DNE_LSB 31
#define USB_GI2CCTL_BSY_DNE_RESET 0x0
#define USB_GI2CCTL_RW_BITS 30:30
#define USB_GI2CCTL_RW_SET 0x40000000
#define USB_GI2CCTL_RW_CLR 0xbfffffff
#define USB_GI2CCTL_RW_MSB 30
#define USB_GI2CCTL_RW_LSB 30
#define USB_GI2CCTL_RW_RESET 0x0
#define USB_GI2CCTL_DAT_SE0_BITS 28:28
#define USB_GI2CCTL_DAT_SE0_SET 0x10000000
#define USB_GI2CCTL_DAT_SE0_CLR 0xefffffff
#define USB_GI2CCTL_DAT_SE0_MSB 28
#define USB_GI2CCTL_DAT_SE0_LSB 28
#define USB_GI2CCTL_DAT_SE0_RESET 0x0
#define USB_GI2CCTL_DEV_ADR_BITS 27:26
#define USB_GI2CCTL_DEV_ADR_SET 0x0c000000
#define USB_GI2CCTL_DEV_ADR_CLR 0xf3ffffff
#define USB_GI2CCTL_DEV_ADR_MSB 27
#define USB_GI2CCTL_DEV_ADR_LSB 26
#define USB_GI2CCTL_DEV_ADR_RESET 0x0
#define USB_GI2CCTL_SUSP_CTL_BITS 25:25
#define USB_GI2CCTL_SUSP_CTL_SET 0x02000000
#define USB_GI2CCTL_SUSP_CTL_CLR 0xfdffffff
#define USB_GI2CCTL_SUSP_CTL_MSB 25
#define USB_GI2CCTL_SUSP_CTL_LSB 25
#define USB_GI2CCTL_SUSP_CTL_RESET 0x0
#define USB_GI2CCTL_EN_BITS 23:23
#define USB_GI2CCTL_EN_SET 0x00800000
#define USB_GI2CCTL_EN_CLR 0xff7fffff
#define USB_GI2CCTL_EN_MSB 23
#define USB_GI2CCTL_EN_LSB 23
#define USB_GI2CCTL_EN_RESET 0x0
#define USB_GI2CCTL_ADDR_BITS 22:16
#define USB_GI2CCTL_ADDR_SET 0x007f0000
#define USB_GI2CCTL_ADDR_CLR 0xff80ffff
#define USB_GI2CCTL_ADDR_MSB 22
#define USB_GI2CCTL_ADDR_LSB 16
#define USB_GI2CCTL_ADDR_RESET 0x0
#define USB_GI2CCTL_REG_ADDR_BITS 15:8
#define USB_GI2CCTL_REG_ADDR_SET 0x0000ff00
#define USB_GI2CCTL_REG_ADDR_CLR 0xffff00ff
#define USB_GI2CCTL_REG_ADDR_MSB 15
#define USB_GI2CCTL_REG_ADDR_LSB 8
#define USB_GI2CCTL_REG_ADDR_RESET 0x0
#define USB_GI2CCTL_RW_DATA_BITS 7:0
#define USB_GI2CCTL_RW_DATA_SET 0x000000ff
#define USB_GI2CCTL_RW_DATA_CLR 0xffffff00
#define USB_GI2CCTL_RW_DATA_MSB 7
#define USB_GI2CCTL_RW_DATA_LSB 0
#define USB_GI2CCTL_RW_DATA_RESET 0x0
#define USB_GPVNDCTL HW_REGISTER_RW( 0x7e980034 )
#define USB_GPVNDCTL_MASK 0x8e7f3fff
#define USB_GPVNDCTL_WIDTH 32
#define USB_GPVNDCTL_DIS_ULPI_DRVR_BITS 31:31
#define USB_GPVNDCTL_DIS_ULPI_DRVR_SET 0x80000000
#define USB_GPVNDCTL_DIS_ULPI_DRVR_CLR 0x7fffffff
#define USB_GPVNDCTL_DIS_ULPI_DRVR_MSB 31
#define USB_GPVNDCTL_DIS_ULPI_DRVR_LSB 31
#define USB_GPVNDCTL_DIS_ULPI_DRVR_RESET 0x0
#define USB_GPVNDCTL_STS_DONE_BITS 27:27
#define USB_GPVNDCTL_STS_DONE_SET 0x08000000
#define USB_GPVNDCTL_STS_DONE_CLR 0xf7ffffff
#define USB_GPVNDCTL_STS_DONE_MSB 27
#define USB_GPVNDCTL_STS_DONE_LSB 27
#define USB_GPVNDCTL_STS_DONE_RESET 0x0
#define USB_GPVNDCTL_STS_BSY_BITS 26:26
#define USB_GPVNDCTL_STS_BSY_SET 0x04000000
#define USB_GPVNDCTL_STS_BSY_CLR 0xfbffffff
#define USB_GPVNDCTL_STS_BSY_MSB 26
#define USB_GPVNDCTL_STS_BSY_LSB 26
#define USB_GPVNDCTL_STS_BSY_RESET 0x0
#define USB_GPVNDCTL_NEW_REG_REQ_BITS 25:25
#define USB_GPVNDCTL_NEW_REG_REQ_SET 0x02000000
#define USB_GPVNDCTL_NEW_REG_REQ_CLR 0xfdffffff
#define USB_GPVNDCTL_NEW_REG_REQ_MSB 25
#define USB_GPVNDCTL_NEW_REG_REQ_LSB 25
#define USB_GPVNDCTL_NEW_REG_REQ_RESET 0x0
#define USB_GPVNDCTL_REG_WR_BITS 22:22
#define USB_GPVNDCTL_REG_WR_SET 0x00400000
#define USB_GPVNDCTL_REG_WR_CLR 0xffbfffff
#define USB_GPVNDCTL_REG_WR_MSB 22
#define USB_GPVNDCTL_REG_WR_LSB 22
#define USB_GPVNDCTL_REG_WR_RESET 0x0
#define USB_GPVNDCTL_REG_ADDR_BITS 21:16
#define USB_GPVNDCTL_REG_ADDR_SET 0x003f0000
#define USB_GPVNDCTL_REG_ADDR_CLR 0xffc0ffff
#define USB_GPVNDCTL_REG_ADDR_MSB 21
#define USB_GPVNDCTL_REG_ADDR_LSB 16
#define USB_GPVNDCTL_REG_ADDR_RESET 0x0
#define USB_GPVNDCTL_CTRL_UTMI_BITS 11:8
#define USB_GPVNDCTL_CTRL_UTMI_SET 0x00000f00
#define USB_GPVNDCTL_CTRL_UTMI_CLR 0xfffff0ff
#define USB_GPVNDCTL_CTRL_UTMI_MSB 11
#define USB_GPVNDCTL_CTRL_UTMI_LSB 8
#define USB_GPVNDCTL_CTRL_UTMI_RESET 0x0
#define USB_GPVNDCTL_CTRL_ULPI_BITS 13:8
#define USB_GPVNDCTL_CTRL_ULPI_SET 0x00003f00
#define USB_GPVNDCTL_CTRL_ULPI_CLR 0xffffc0ff
#define USB_GPVNDCTL_CTRL_ULPI_MSB 13
#define USB_GPVNDCTL_CTRL_ULPI_LSB 8
#define USB_GPVNDCTL_CTRL_ULPI_RESET 0x0
#define USB_GPVNDCTL_REG_DATA_BITS 7:0
#define USB_GPVNDCTL_REG_DATA_SET 0x000000ff
#define USB_GPVNDCTL_REG_DATA_CLR 0xffffff00
#define USB_GPVNDCTL_REG_DATA_MSB 7
#define USB_GPVNDCTL_REG_DATA_LSB 0
#define USB_GPVNDCTL_REG_DATA_RESET 0x0
#define USB_GGPIO HW_REGISTER_RW( 0x7e980038 )
#define USB_GGPIO_MASK 0xffffffff
#define USB_GGPIO_WIDTH 32
#define USB_GGPIO_GPO_BITS 31:16
#define USB_GGPIO_GPO_SET 0xffff0000
#define USB_GGPIO_GPO_CLR 0x0000ffff
#define USB_GGPIO_GPO_MSB 31
#define USB_GGPIO_GPO_LSB 16
#define USB_GGPIO_GPO_RESET 0x0
#define USB_GGPIO_GPI_BITS 15:0
#define USB_GGPIO_GPI_SET 0x0000ffff
#define USB_GGPIO_GPI_CLR 0xffff0000
#define USB_GGPIO_GPI_MSB 15
#define USB_GGPIO_GPI_LSB 0
#define USB_GGPIO_GPI_RESET 0x0
#define USB_GUID HW_REGISTER_RW( 0x7e98003c )
#define USB_GUID_MASK 0xffffffff
#define USB_GUID_WIDTH 32
#define USB_GSNPSID HW_REGISTER_RW( 0x7e980040 )
#define USB_GSNPSID_MASK 0xffffffff
#define USB_GSNPSID_WIDTH 32
#define USB_GHWCFG1 HW_REGISTER_RW( 0x7e980044 )
#define USB_GHWCFG1_MASK 0xffffffff
#define USB_GHWCFG1_WIDTH 32
#define USB_GHWCFG2 HW_REGISTER_RW( 0x7e980048 )
#define USB_GHWCFG2_MASK 0x7fcfffff
#define USB_GHWCFG2_WIDTH 31
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_BITS 30:26
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_SET 0x7c000000
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_CLR 0x83ffffff
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_MSB 30
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_LSB 26
#define USB_GHWCFG2_TOKEN_QUEUE_DEPTH_RESET 0x0
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_BITS 25:24
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_SET 0x03000000
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_CLR 0xfcffffff
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_MSB 25
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_LSB 24
#define USB_GHWCFG2_PERIO_TX_QUEUE_DEPTH_RESET 0x0
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_BITS 23:22
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_SET 0x00c00000
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_CLR 0xff3fffff
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_MSB 23
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_LSB 22
#define USB_GHWCFG2_NPERIO_TX_QUEUE_DEPTH_RESET 0x0
#define USB_GHWCFG2_DFIFO_DYNAMIC_BITS 19:19
#define USB_GHWCFG2_DFIFO_DYNAMIC_SET 0x00080000
#define USB_GHWCFG2_DFIFO_DYNAMIC_CLR 0xfff7ffff
#define USB_GHWCFG2_DFIFO_DYNAMIC_MSB 19
#define USB_GHWCFG2_DFIFO_DYNAMIC_LSB 19
#define USB_GHWCFG2_DFIFO_DYNAMIC_RESET 0x0
#define USB_GHWCFG2_EN_PERIO_HOST_BITS 18:18
#define USB_GHWCFG2_EN_PERIO_HOST_SET 0x00040000
#define USB_GHWCFG2_EN_PERIO_HOST_CLR 0xfffbffff
#define USB_GHWCFG2_EN_PERIO_HOST_MSB 18
#define USB_GHWCFG2_EN_PERIO_HOST_LSB 18
#define USB_GHWCFG2_EN_PERIO_HOST_RESET 0x0
#define USB_GHWCFG2_NUM_HOST_CHAN_BITS 14:17
#define USB_GHWCFG2_NUM_HOST_CHAN_SET 0x0000000000
#define USB_GHWCFG2_NUM_HOST_CHAN_CLR 0xffffffff11
#define USB_GHWCFG2_NUM_HOST_CHAN_MSB 14
#define USB_GHWCFG2_NUM_HOST_CHAN_LSB 17
#define USB_GHWCFG2_NUM_HOST_CHAN_RESET 0x0
#define USB_GHWCFG2_NUM_EPS_BITS 10:13
#define USB_GHWCFG2_NUM_EPS_SET 0x0000000000
#define USB_GHWCFG2_NUM_EPS_CLR 0xffffffff11
#define USB_GHWCFG2_NUM_EPS_MSB 10
#define USB_GHWCFG2_NUM_EPS_LSB 13
#define USB_GHWCFG2_NUM_EPS_RESET 0x0
#define USB_GHWCFG2_FSPHY_INTERFACE_BITS 9:8
#define USB_GHWCFG2_FSPHY_INTERFACE_SET 0x00000300
#define USB_GHWCFG2_FSPHY_INTERFACE_CLR 0xfffffcff
#define USB_GHWCFG2_FSPHY_INTERFACE_MSB 9
#define USB_GHWCFG2_FSPHY_INTERFACE_LSB 8
#define USB_GHWCFG2_FSPHY_INTERFACE_RESET 0x0
#define USB_GHWCFG2_HSPHY_INTERFACE_BITS 7:6
#define USB_GHWCFG2_HSPHY_INTERFACE_SET 0x000000c0
#define USB_GHWCFG2_HSPHY_INTERFACE_CLR 0xffffff3f
#define USB_GHWCFG2_HSPHY_INTERFACE_MSB 7
#define USB_GHWCFG2_HSPHY_INTERFACE_LSB 6
#define USB_GHWCFG2_HSPHY_INTERFACE_RESET 0x0
#define USB_GHWCFG2_SINGLE_POINT_BITS 5:5
#define USB_GHWCFG2_SINGLE_POINT_SET 0x00000020
#define USB_GHWCFG2_SINGLE_POINT_CLR 0xffffffdf
#define USB_GHWCFG2_SINGLE_POINT_MSB 5
#define USB_GHWCFG2_SINGLE_POINT_LSB 5
#define USB_GHWCFG2_SINGLE_POINT_RESET 0x0
#define USB_GHWCFG2_ARCHITECTURE_BITS 4:3
#define USB_GHWCFG2_ARCHITECTURE_SET 0x00000018
#define USB_GHWCFG2_ARCHITECTURE_CLR 0xffffffe7
#define USB_GHWCFG2_ARCHITECTURE_MSB 4
#define USB_GHWCFG2_ARCHITECTURE_LSB 3
#define USB_GHWCFG2_ARCHITECTURE_RESET 0x0
#define USB_GHWCFG2_MODE_BITS 2:0
#define USB_GHWCFG2_MODE_SET 0x00000007
#define USB_GHWCFG2_MODE_CLR 0xfffffff8
#define USB_GHWCFG2_MODE_MSB 2
#define USB_GHWCFG2_MODE_LSB 0
#define USB_GHWCFG2_MODE_RESET 0x0
#define USB_GHWCFG3 HW_REGISTER_RW( 0x7e98004c )
#define USB_GHWCFG3_MASK 0xffff0fff
#define USB_GHWCFG3_WIDTH 32
#define USB_GHWCFG3_DFIFO_DEPTH_BITS 31:16
#define USB_GHWCFG3_DFIFO_DEPTH_SET 0xffff0000
#define USB_GHWCFG3_DFIFO_DEPTH_CLR 0x0000ffff
#define USB_GHWCFG3_DFIFO_DEPTH_MSB 31
#define USB_GHWCFG3_DFIFO_DEPTH_LSB 16
#define USB_GHWCFG3_DFIFO_DEPTH_RESET 0x0
#define USB_GHWCFG3_SYNC_RESET_TYPE_BITS 11:11
#define USB_GHWCFG3_SYNC_RESET_TYPE_SET 0x00000800
#define USB_GHWCFG3_SYNC_RESET_TYPE_CLR 0xfffff7ff
#define USB_GHWCFG3_SYNC_RESET_TYPE_MSB 11
#define USB_GHWCFG3_SYNC_RESET_TYPE_LSB 11
#define USB_GHWCFG3_SYNC_RESET_TYPE_RESET 0x0
#define USB_GHWCFG3_RM_OPT_FEATURES_BITS 10:10
#define USB_GHWCFG3_RM_OPT_FEATURES_SET 0x00000400
#define USB_GHWCFG3_RM_OPT_FEATURES_CLR 0xfffffbff
#define USB_GHWCFG3_RM_OPT_FEATURES_MSB 10
#define USB_GHWCFG3_RM_OPT_FEATURES_LSB 10
#define USB_GHWCFG3_RM_OPT_FEATURES_RESET 0x0
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_BITS 9:9
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_SET 0x00000200
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_CLR 0xfffffdff
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_MSB 9
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_LSB 9
#define USB_GHWCFG3_VENDOR_CTL_INTERFACE_RESET 0x0
#define USB_GHWCFG3_I2C_INTERFACE_BITS 8:8
#define USB_GHWCFG3_I2C_INTERFACE_SET 0x00000100
#define USB_GHWCFG3_I2C_INTERFACE_CLR 0xfffffeff
#define USB_GHWCFG3_I2C_INTERFACE_MSB 8
#define USB_GHWCFG3_I2C_INTERFACE_LSB 8
#define USB_GHWCFG3_I2C_INTERFACE_RESET 0x0
#define USB_GHWCFG3_MODE_BITS 7:7
#define USB_GHWCFG3_MODE_SET 0x00000080
#define USB_GHWCFG3_MODE_CLR 0xffffff7f
#define USB_GHWCFG3_MODE_MSB 7
#define USB_GHWCFG3_MODE_LSB 7
#define USB_GHWCFG3_MODE_RESET 0x0
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_BITS 6:4
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_SET 0x00000070
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_CLR 0xffffff8f
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_MSB 6
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_LSB 4
#define USB_GHWCFG3_PACKET_COUNT_WIDTH_RESET 0x0
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_BITS 3:0
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_SET 0x0000000f
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_CLR 0xfffffff0
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_MSB 3
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_LSB 0
#define USB_GHWCFG3_TRANS_COUNT_WIDTH_RESET 0x0
#define USB_GHWCFG4 HW_REGISTER_RW( 0x7e980050 )
#define USB_GHWCFG4_MASK 0xffffc03f
#define USB_GHWCFG4_WIDTH 32
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_BITS 31:31
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_SET 0x80000000
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_CLR 0x7fffffff
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_MSB 31
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_LSB 31
#define USB_GHWCFG4_EN_DESC_DMA_DYNAMIC_RESET 0x0
#define USB_GHWCFG4_EN_DESC_DMA_BITS 30:30
#define USB_GHWCFG4_EN_DESC_DMA_SET 0x40000000
#define USB_GHWCFG4_EN_DESC_DMA_CLR 0xbfffffff
#define USB_GHWCFG4_EN_DESC_DMA_MSB 30
#define USB_GHWCFG4_EN_DESC_DMA_LSB 30
#define USB_GHWCFG4_EN_DESC_DMA_RESET 0x0
#define USB_GHWCFG4_NUM_IN_EPS_BITS 27:26
#define USB_GHWCFG4_NUM_IN_EPS_SET 0x0c000000
#define USB_GHWCFG4_NUM_IN_EPS_CLR 0xf3ffffff
#define USB_GHWCFG4_NUM_IN_EPS_MSB 27
#define USB_GHWCFG4_NUM_IN_EPS_LSB 26
#define USB_GHWCFG4_NUM_IN_EPS_RESET 0x0
#define USB_GHWCFG4_EN_DED_TX_FIFO_BITS 25:25
#define USB_GHWCFG4_EN_DED_TX_FIFO_SET 0x02000000
#define USB_GHWCFG4_EN_DED_TX_FIFO_CLR 0xfdffffff
#define USB_GHWCFG4_EN_DED_TX_FIFO_MSB 25
#define USB_GHWCFG4_EN_DED_TX_FIFO_LSB 25
#define USB_GHWCFG4_EN_DED_TX_FIFO_RESET 0x0
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_BITS 24:24
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_SET 0x01000000
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_CLR 0xfeffffff
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_MSB 24
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_LSB 24
#define USB_GHWCFG4_EN_SESSIONEND_FILTER_RESET 0x0
#define USB_GHWCFG4_EN_B_VALID_FILTER_BITS 23:23
#define USB_GHWCFG4_EN_B_VALID_FILTER_SET 0x00800000
#define USB_GHWCFG4_EN_B_VALID_FILTER_CLR 0xff7fffff
#define USB_GHWCFG4_EN_B_VALID_FILTER_MSB 23
#define USB_GHWCFG4_EN_B_VALID_FILTER_LSB 23
#define USB_GHWCFG4_EN_B_VALID_FILTER_RESET 0x0
#define USB_GHWCFG4_EN_A_VALID_FILTER_BITS 22:22
#define USB_GHWCFG4_EN_A_VALID_FILTER_SET 0x00400000
#define USB_GHWCFG4_EN_A_VALID_FILTER_CLR 0xffbfffff
#define USB_GHWCFG4_EN_A_VALID_FILTER_MSB 22
#define USB_GHWCFG4_EN_A_VALID_FILTER_LSB 22
#define USB_GHWCFG4_EN_A_VALID_FILTER_RESET 0x0
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_BITS 21:21
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_SET 0x00200000
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_CLR 0xffdfffff
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_MSB 21
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_LSB 21
#define USB_GHWCFG4_EN_VBUSVALID_FILTER_RESET 0x0
#define USB_GHWCFG4_EN_IDDIG_FILTER_BITS 20:20
#define USB_GHWCFG4_EN_IDDIG_FILTER_SET 0x00100000
#define USB_GHWCFG4_EN_IDDIG_FILTER_CLR 0xffefffff
#define USB_GHWCFG4_EN_IDDIG_FILTER_MSB 20
#define USB_GHWCFG4_EN_IDDIG_FILTER_LSB 20
#define USB_GHWCFG4_EN_IDDIG_FILTER_RESET 0x0
#define USB_GHWCFG4_NUM_CRL_EPS_BITS 19:16
#define USB_GHWCFG4_NUM_CRL_EPS_SET 0x000f0000
#define USB_GHWCFG4_NUM_CRL_EPS_CLR 0xfff0ffff
#define USB_GHWCFG4_NUM_CRL_EPS_MSB 19
#define USB_GHWCFG4_NUM_CRL_EPS_LSB 16
#define USB_GHWCFG4_NUM_CRL_EPS_RESET 0x0
#define USB_GHWCFG4_HSPHY_DWIDTH_BITS 15:14
#define USB_GHWCFG4_HSPHY_DWIDTH_SET 0x0000c000
#define USB_GHWCFG4_HSPHY_DWIDTH_CLR 0xffff3fff
#define USB_GHWCFG4_HSPHY_DWIDTH_MSB 15
#define USB_GHWCFG4_HSPHY_DWIDTH_LSB 14
#define USB_GHWCFG4_HSPHY_DWIDTH_RESET 0x0
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_BITS 5:5
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_SET 0x00000020
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_CLR 0xffffffdf
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_MSB 5
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_LSB 5
#define USB_GHWCFG4_MIN_AHB_FREQ_LESSTHAN_60_RESET 0x0
#define USB_GHWCFG4_EN_PWROPT_BITS 4:4
#define USB_GHWCFG4_EN_PWROPT_SET 0x00000010
#define USB_GHWCFG4_EN_PWROPT_CLR 0xffffffef
#define USB_GHWCFG4_EN_PWROPT_MSB 4
#define USB_GHWCFG4_EN_PWROPT_LSB 4
#define USB_GHWCFG4_EN_PWROPT_RESET 0x0
#define USB_GHWCFG4_NUM_PERIO_EPS_BITS 3:0
#define USB_GHWCFG4_NUM_PERIO_EPS_SET 0x0000000f
#define USB_GHWCFG4_NUM_PERIO_EPS_CLR 0xfffffff0
#define USB_GHWCFG4_NUM_PERIO_EPS_MSB 3
#define USB_GHWCFG4_NUM_PERIO_EPS_LSB 0
#define USB_GHWCFG4_NUM_PERIO_EPS_RESET 0x0
#define USB_GLPMCFG HW_REGISTER_RW( 0x7e980054 )
#define USB_GLPMCFG_MASK 0xffffffff
#define USB_GLPMCFG_WIDTH 32
#define USB_GAXIDEV HW_REGISTER_RW( 0x7e980054 )
#define USB_GAXIDEV_MASK 0xffffffff
#define USB_GAXIDEV_WIDTH 32
#define USB_GMDIOCSR HW_REGISTER_RW( 0x7e980080 )
#define USB_GMDIOCSR_MASK 0x0000ffff
#define USB_GMDIOCSR_WIDTH 16
#define USB_GMDIOGEN HW_REGISTER_RW( 0x7e980084 )
#define USB_GMDIOGEN_MASK 0xffffffff
#define USB_GMDIOGEN_WIDTH 32
#define USB_GVBUSDRV HW_REGISTER_RW( 0x7e980088 )
#define USB_GVBUSDRV_MASK 0x0000ffff
#define USB_GVBUSDRV_WIDTH 16
#define USB_HPTXFSIZ HW_REGISTER_RW( 0x7e980100 )
#define USB_HPTXFSIZ_MASK 0xffffffff
#define USB_HPTXFSIZ_WIDTH 32
#define USB_DPTXFSIZ1 HW_REGISTER_RW( 0x7e980104 )
#define USB_DPTXFSIZ1_MASK 0xffffffff
#define USB_DPTXFSIZ1_WIDTH 32
#define USB_DPTXFSIZ2 HW_REGISTER_RW( 0x7e980108 )
#define USB_DPTXFSIZ2_MASK 0xffffffff
#define USB_DPTXFSIZ2_WIDTH 32
#define USB_DPTXFSIZ3 HW_REGISTER_RW( 0x7e98010c )
#define USB_DPTXFSIZ3_MASK 0xffffffff
#define USB_DPTXFSIZ3_WIDTH 32
#define USB_DPTXFSIZ4 HW_REGISTER_RW( 0x7e980110 )
#define USB_DPTXFSIZ4_MASK 0xffffffff
#define USB_DPTXFSIZ4_WIDTH 32
#define USB_DPTXFSIZ5 HW_REGISTER_RW( 0x7e980114 )
#define USB_DPTXFSIZ5_MASK 0xffffffff
#define USB_DPTXFSIZ5_WIDTH 32
#define USB_DPTXFSIZ6 HW_REGISTER_RW( 0x7e980118 )
#define USB_DPTXFSIZ6_MASK 0xffffffff
#define USB_DPTXFSIZ6_WIDTH 32
#define USB_DPTXFSIZ7 HW_REGISTER_RW( 0x7e98011c )
#define USB_DPTXFSIZ7_MASK 0xffffffff
#define USB_DPTXFSIZ7_WIDTH 32
#define USB_DPTXFSIZ8 HW_REGISTER_RW( 0x7e980120 )
#define USB_DPTXFSIZ8_MASK 0xffffffff
#define USB_DPTXFSIZ8_WIDTH 32
#define USB_DPTXFSIZ9 HW_REGISTER_RW( 0x7e980124 )
#define USB_DPTXFSIZ9_MASK 0xffffffff
#define USB_DPTXFSIZ9_WIDTH 32
#define USB_DPTXFSIZ10 HW_REGISTER_RW( 0x7e980128 )
#define USB_DPTXFSIZ10_MASK 0xffffffff
#define USB_DPTXFSIZ10_WIDTH 32
#define USB_DPTXFSIZ11 HW_REGISTER_RW( 0x7e98012c )
#define USB_DPTXFSIZ11_MASK 0xffffffff
#define USB_DPTXFSIZ11_WIDTH 32
#define USB_DPTXFSIZ12 HW_REGISTER_RW( 0x7e980130 )
#define USB_DPTXFSIZ12_MASK 0xffffffff
#define USB_DPTXFSIZ12_WIDTH 32
#define USB_DPTXFSIZ13 HW_REGISTER_RW( 0x7e980134 )
#define USB_DPTXFSIZ13_MASK 0xffffffff
#define USB_DPTXFSIZ13_WIDTH 32
#define USB_DPTXFSIZ14 HW_REGISTER_RW( 0x7e980138 )
#define USB_DPTXFSIZ14_MASK 0xffffffff
#define USB_DPTXFSIZ14_WIDTH 32
#define USB_DPTXFSIZ15 HW_REGISTER_RW( 0x7e98013c )
#define USB_DPTXFSIZ15_MASK 0xffffffff
#define USB_DPTXFSIZ15_WIDTH 32
#define USB_DIEPTXF1 HW_REGISTER_RW( 0x7e980104 )
#define USB_DIEPTXF1_MASK 0xffffffff
#define USB_DIEPTXF1_WIDTH 32
#define USB_DIEPTXF1_FIFO_SIZE_BITS 31:16
#define USB_DIEPTXF1_FIFO_SIZE_SET 0xffff0000
#define USB_DIEPTXF1_FIFO_SIZE_CLR 0x0000ffff
#define USB_DIEPTXF1_FIFO_SIZE_MSB 31
#define USB_DIEPTXF1_FIFO_SIZE_LSB 16
#define USB_DIEPTXF1_FIFO_SIZE_RESET 0x0
#define USB_DIEPTXF1_FIFO_STADDR_BITS 15:0
#define USB_DIEPTXF1_FIFO_STADDR_SET 0x0000ffff
#define USB_DIEPTXF1_FIFO_STADDR_CLR 0xffff0000
#define USB_DIEPTXF1_FIFO_STADDR_MSB 15
#define USB_DIEPTXF1_FIFO_STADDR_LSB 0
#define USB_DIEPTXF1_FIFO_STADDR_RESET 0x0
#define USB_DIEPTXF2 HW_REGISTER_RW( 0x7e980108 )
#define USB_DIEPTXF2_MASK 0xffffffff
#define USB_DIEPTXF2_WIDTH 32
#define USB_DIEPTXF3 HW_REGISTER_RW( 0x7e98010c )
#define USB_DIEPTXF3_MASK 0xffffffff
#define USB_DIEPTXF3_WIDTH 32
#define USB_DIEPTXF4 HW_REGISTER_RW( 0x7e980110 )
#define USB_DIEPTXF4_MASK 0xffffffff
#define USB_DIEPTXF4_WIDTH 32
#define USB_DIEPTXF5 HW_REGISTER_RW( 0x7e980114 )
#define USB_DIEPTXF5_MASK 0xffffffff
#define USB_DIEPTXF5_WIDTH 32
#define USB_DIEPTXF6 HW_REGISTER_RW( 0x7e980118 )
#define USB_DIEPTXF6_MASK 0xffffffff
#define USB_DIEPTXF6_WIDTH 32
#define USB_DIEPTXF7 HW_REGISTER_RW( 0x7e98011c )
#define USB_DIEPTXF7_MASK 0xffffffff
#define USB_DIEPTXF7_WIDTH 32
#define USB_DIEPTXF8 HW_REGISTER_RW( 0x7e980120 )
#define USB_DIEPTXF8_MASK 0xffffffff
#define USB_DIEPTXF8_WIDTH 32
#define USB_DIEPTXF9 HW_REGISTER_RW( 0x7e980124 )
#define USB_DIEPTXF9_MASK 0xffffffff
#define USB_DIEPTXF9_WIDTH 32
#define USB_DIEPTXF10 HW_REGISTER_RW( 0x7e980128 )
#define USB_DIEPTXF10_MASK 0xffffffff
#define USB_DIEPTXF10_WIDTH 32
#define USB_DIEPTXF11 HW_REGISTER_RW( 0x7e98012c )
#define USB_DIEPTXF11_MASK 0xffffffff
#define USB_DIEPTXF11_WIDTH 32
#define USB_DIEPTXF12 HW_REGISTER_RW( 0x7e980130 )
#define USB_DIEPTXF12_MASK 0xffffffff
#define USB_DIEPTXF12_WIDTH 32
#define USB_DIEPTXF13 HW_REGISTER_RW( 0x7e980134 )
#define USB_DIEPTXF13_MASK 0xffffffff
#define USB_DIEPTXF13_WIDTH 32
#define USB_DIEPTXF14 HW_REGISTER_RW( 0x7e980138 )
#define USB_DIEPTXF14_MASK 0xffffffff
#define USB_DIEPTXF14_WIDTH 32
#define USB_DIEPTXF15 HW_REGISTER_RW( 0x7e98013c )
#define USB_DIEPTXF15_MASK 0xffffffff
#define USB_DIEPTXF15_WIDTH 32
#define USB_HCFG HW_REGISTER_RW( 0x7e980400 )
#define USB_HCFG_MASK 0x00000007
#define USB_HCFG_WIDTH 3
#define USB_HCFG_LS_SUPP_BITS 2:2
#define USB_HCFG_LS_SUPP_SET 0x00000004
#define USB_HCFG_LS_SUPP_CLR 0xfffffffb
#define USB_HCFG_LS_SUPP_MSB 2
#define USB_HCFG_LS_SUPP_LSB 2
#define USB_HCFG_LS_SUPP_RESET 0x0
#define USB_HCFG_LS_PHY_CLK_SEL_BITS 1:0
#define USB_HCFG_LS_PHY_CLK_SEL_SET 0x00000003
#define USB_HCFG_LS_PHY_CLK_SEL_CLR 0xfffffffc
#define USB_HCFG_LS_PHY_CLK_SEL_MSB 1
#define USB_HCFG_LS_PHY_CLK_SEL_LSB 0
#define USB_HCFG_LS_PHY_CLK_SEL_RESET 0x0
#define USB_HFIR HW_REGISTER_RW( 0x7e980404 )
#define USB_HFIR_MASK 0x0000ffff
#define USB_HFIR_WIDTH 16
#define USB_HFIR_IN_BITS 15:0
#define USB_HFIR_IN_SET 0x0000ffff
#define USB_HFIR_IN_CLR 0xffff0000
#define USB_HFIR_IN_MSB 15
#define USB_HFIR_IN_LSB 0
#define USB_HFIR_IN_RESET 0x0
#define USB_HFNUM HW_REGISTER_RW( 0x7e980408 )
#define USB_HFNUM_MASK 0xffffffff
#define USB_HFNUM_WIDTH 32
#define USB_HFNUM_REM_BITS 31:16
#define USB_HFNUM_REM_SET 0xffff0000
#define USB_HFNUM_REM_CLR 0x0000ffff
#define USB_HFNUM_REM_MSB 31
#define USB_HFNUM_REM_LSB 16
#define USB_HFNUM_REM_RESET 0x0
#define USB_HFNUM_NUM_BITS 15:0
#define USB_HFNUM_NUM_SET 0x0000ffff
#define USB_HFNUM_NUM_CLR 0xffff0000
#define USB_HFNUM_NUM_MSB 15
#define USB_HFNUM_NUM_LSB 0
#define USB_HFNUM_NUM_RESET 0x0
#define USB_HPTXSTS HW_REGISTER_RW( 0x7e980410 )
#define USB_HPTXSTS_MASK 0xffffffff
#define USB_HPTXSTS_WIDTH 32
#define USB_HPTXSTS_HPTXQTOP_BITS 31:24
#define USB_HPTXSTS_HPTXQTOP_SET 0xff000000
#define USB_HPTXSTS_HPTXQTOP_CLR 0x00ffffff
#define USB_HPTXSTS_HPTXQTOP_MSB 31
#define USB_HPTXSTS_HPTXQTOP_LSB 24
#define USB_HPTXSTS_HPTXQTOP_RESET 0x0
#define USB_HPTXSTS_HPTXQSPCAVAIL_BITS 23:16
#define USB_HPTXSTS_HPTXQSPCAVAIL_SET 0x00ff0000
#define USB_HPTXSTS_HPTXQSPCAVAIL_CLR 0xff00ffff
#define USB_HPTXSTS_HPTXQSPCAVAIL_MSB 23
#define USB_HPTXSTS_HPTXQSPCAVAIL_LSB 16
#define USB_HPTXSTS_HPTXQSPCAVAIL_RESET 0x0
#define USB_HPTXSTS_HPTXFSPCAVAIL_BITS 15:0
#define USB_HPTXSTS_HPTXFSPCAVAIL_SET 0x0000ffff
#define USB_HPTXSTS_HPTXFSPCAVAIL_CLR 0xffff0000
#define USB_HPTXSTS_HPTXFSPCAVAIL_MSB 15
#define USB_HPTXSTS_HPTXFSPCAVAIL_LSB 0
#define USB_HPTXSTS_HPTXFSPCAVAIL_RESET 0x0
#define USB_HAINT HW_REGISTER_RW( 0x7e980414 )
#define USB_HAINT_MASK 0xffffffff
#define USB_HAINT_WIDTH 32
#define USB_HAINTMSK HW_REGISTER_RW( 0x7e980418 )
#define USB_HAINTMSK_MASK 0xffffffff
#define USB_HAINTMSK_WIDTH 32
#define USB_HPRT HW_REGISTER_RW( 0x7e980440 )
#define USB_HPRT_MASK 0x0007fdff
#define USB_HPRT_WIDTH 19
#define USB_HPRT_SPD_BITS 18:17
#define USB_HPRT_SPD_SET 0x00060000
#define USB_HPRT_SPD_CLR 0xfff9ffff
#define USB_HPRT_SPD_MSB 18
#define USB_HPRT_SPD_LSB 17
#define USB_HPRT_SPD_RESET 0x0
#define USB_HPRT_TST_CTL_BITS 16:13
#define USB_HPRT_TST_CTL_SET 0x0001e000
#define USB_HPRT_TST_CTL_CLR 0xfffe1fff
#define USB_HPRT_TST_CTL_MSB 16
#define USB_HPRT_TST_CTL_LSB 13
#define USB_HPRT_TST_CTL_RESET 0x0
#define USB_HPRT_PWR_BITS 12:12
#define USB_HPRT_PWR_SET 0x00001000
#define USB_HPRT_PWR_CLR 0xffffefff
#define USB_HPRT_PWR_MSB 12
#define USB_HPRT_PWR_LSB 12
#define USB_HPRT_PWR_RESET 0x0
#define USB_HPRT_LN_STS_BITS 11:10
#define USB_HPRT_LN_STS_SET 0x00000c00
#define USB_HPRT_LN_STS_CLR 0xfffff3ff
#define USB_HPRT_LN_STS_MSB 11
#define USB_HPRT_LN_STS_LSB 10
#define USB_HPRT_LN_STS_RESET 0x0
#define USB_HPRT_RST_BITS 8:8
#define USB_HPRT_RST_SET 0x00000100
#define USB_HPRT_RST_CLR 0xfffffeff
#define USB_HPRT_RST_MSB 8
#define USB_HPRT_RST_LSB 8
#define USB_HPRT_RST_RESET 0x0
#define USB_HPRT_SUSP_BITS 7:7
#define USB_HPRT_SUSP_SET 0x00000080
#define USB_HPRT_SUSP_CLR 0xffffff7f
#define USB_HPRT_SUSP_MSB 7
#define USB_HPRT_SUSP_LSB 7
#define USB_HPRT_SUSP_RESET 0x0
#define USB_HPRT_RES_BITS 6:6
#define USB_HPRT_RES_SET 0x00000040
#define USB_HPRT_RES_CLR 0xffffffbf
#define USB_HPRT_RES_MSB 6
#define USB_HPRT_RES_LSB 6
#define USB_HPRT_RES_RESET 0x0
#define USB_HPRT_OVR_CURR_CHNG_BITS 5:5
#define USB_HPRT_OVR_CURR_CHNG_SET 0x00000020
#define USB_HPRT_OVR_CURR_CHNG_CLR 0xffffffdf
#define USB_HPRT_OVR_CURR_CHNG_MSB 5
#define USB_HPRT_OVR_CURR_CHNG_LSB 5
#define USB_HPRT_OVR_CURR_CHNG_RESET 0x0
#define USB_HPRT_OVR_CURR_ACT_BITS 4:4
#define USB_HPRT_OVR_CURR_ACT_SET 0x00000010
#define USB_HPRT_OVR_CURR_ACT_CLR 0xffffffef
#define USB_HPRT_OVR_CURR_ACT_MSB 4
#define USB_HPRT_OVR_CURR_ACT_LSB 4
#define USB_HPRT_OVR_CURR_ACT_RESET 0x0
#define USB_HPRT_EN_CHNG_BITS 3:3
#define USB_HPRT_EN_CHNG_SET 0x00000008
#define USB_HPRT_EN_CHNG_CLR 0xfffffff7
#define USB_HPRT_EN_CHNG_MSB 3
#define USB_HPRT_EN_CHNG_LSB 3
#define USB_HPRT_EN_CHNG_RESET 0x0
#define USB_HPRT_ENA_BITS 2:2
#define USB_HPRT_ENA_SET 0x00000004
#define USB_HPRT_ENA_CLR 0xfffffffb
#define USB_HPRT_ENA_MSB 2
#define USB_HPRT_ENA_LSB 2
#define USB_HPRT_ENA_RESET 0x0
#define USB_HPRT_CONN_DET_BITS 1:1
#define USB_HPRT_CONN_DET_SET 0x00000002
#define USB_HPRT_CONN_DET_CLR 0xfffffffd
#define USB_HPRT_CONN_DET_MSB 1
#define USB_HPRT_CONN_DET_LSB 1
#define USB_HPRT_CONN_DET_RESET 0x0
#define USB_HPRT_CONN_STS_BITS 0:0
#define USB_HPRT_CONN_STS_SET 0x00000001
#define USB_HPRT_CONN_STS_CLR 0xfffffffe
#define USB_HPRT_CONN_STS_MSB 0
#define USB_HPRT_CONN_STS_LSB 0
#define USB_HPRT_CONN_STS_RESET 0x0
#define USB_HCCHAR0 HW_REGISTER_RW( 0x7e980500 )
#define USB_HCCHAR0_MASK 0xffffffff
#define USB_HCCHAR0_WIDTH 32
#define USB_HCCHAR0_CH_ENA_BITS 31:31
#define USB_HCCHAR0_CH_ENA_SET 0x80000000
#define USB_HCCHAR0_CH_ENA_CLR 0x7fffffff
#define USB_HCCHAR0_CH_ENA_MSB 31
#define USB_HCCHAR0_CH_ENA_LSB 31
#define USB_HCCHAR0_CH_ENA_RESET 0x0
#define USB_HCCHAR0_CH_DIS_BITS 30:30
#define USB_HCCHAR0_CH_DIS_SET 0x40000000
#define USB_HCCHAR0_CH_DIS_CLR 0xbfffffff
#define USB_HCCHAR0_CH_DIS_MSB 30
#define USB_HCCHAR0_CH_DIS_LSB 30
#define USB_HCCHAR0_CH_DIS_RESET 0x0
#define USB_HCCHAR0_ODD_FRM_BITS 29:29
#define USB_HCCHAR0_ODD_FRM_SET 0x20000000
#define USB_HCCHAR0_ODD_FRM_CLR 0xdfffffff
#define USB_HCCHAR0_ODD_FRM_MSB 29
#define USB_HCCHAR0_ODD_FRM_LSB 29
#define USB_HCCHAR0_ODD_FRM_RESET 0x0
#define USB_HCCHAR0_DEV_ADDR_BITS 28:22
#define USB_HCCHAR0_DEV_ADDR_SET 0x1fc00000
#define USB_HCCHAR0_DEV_ADDR_CLR 0xe03fffff
#define USB_HCCHAR0_DEV_ADDR_MSB 28
#define USB_HCCHAR0_DEV_ADDR_LSB 22
#define USB_HCCHAR0_DEV_ADDR_RESET 0x0
#define USB_HCCHAR0_MC_EC_BITS 21:20
#define USB_HCCHAR0_MC_EC_SET 0x00300000
#define USB_HCCHAR0_MC_EC_CLR 0xffcfffff
#define USB_HCCHAR0_MC_EC_MSB 21
#define USB_HCCHAR0_MC_EC_LSB 20
#define USB_HCCHAR0_MC_EC_RESET 0x0
#define USB_HCCHAR0_EP_TYPE_BITS 19:18
#define USB_HCCHAR0_EP_TYPE_SET 0x000c0000
#define USB_HCCHAR0_EP_TYPE_CLR 0xfff3ffff
#define USB_HCCHAR0_EP_TYPE_MSB 19
#define USB_HCCHAR0_EP_TYPE_LSB 18
#define USB_HCCHAR0_EP_TYPE_RESET 0x0
#define USB_HCCHAR0_LSPD_DEV_BITS 17:17
#define USB_HCCHAR0_LSPD_DEV_SET 0x00020000
#define USB_HCCHAR0_LSPD_DEV_CLR 0xfffdffff
#define USB_HCCHAR0_LSPD_DEV_MSB 17
#define USB_HCCHAR0_LSPD_DEV_LSB 17
#define USB_HCCHAR0_LSPD_DEV_RESET 0x0
#define USB_HCCHAR0_EP_DIR_BITS 15:15
#define USB_HCCHAR0_EP_DIR_SET 0x00008000
#define USB_HCCHAR0_EP_DIR_CLR 0xffff7fff
#define USB_HCCHAR0_EP_DIR_MSB 15
#define USB_HCCHAR0_EP_DIR_LSB 15
#define USB_HCCHAR0_EP_DIR_RESET 0x0
#define USB_HCCHAR0_EP_NUM_BITS 14:11
#define USB_HCCHAR0_EP_NUM_SET 0x00007800
#define USB_HCCHAR0_EP_NUM_CLR 0xffff87ff
#define USB_HCCHAR0_EP_NUM_MSB 14
#define USB_HCCHAR0_EP_NUM_LSB 11
#define USB_HCCHAR0_EP_NUM_RESET 0x0
#define USB_HCCHAR0_MPS_BITS 10:0
#define USB_HCCHAR0_MPS_SET 0x000007ff
#define USB_HCCHAR0_MPS_CLR 0xfffff800
#define USB_HCCHAR0_MPS_MSB 10
#define USB_HCCHAR0_MPS_LSB 0
#define USB_HCCHAR0_MPS_RESET 0x0
#define USB_HCSPLT0 HW_REGISTER_RW( 0x7e980504 )
#define USB_HCSPLT0_MASK 0xffffffff
#define USB_HCSPLT0_WIDTH 32
#define USB_HCSPLT0_SPLT_ENA_BITS 31:31
#define USB_HCSPLT0_SPLT_ENA_SET 0x80000000
#define USB_HCSPLT0_SPLT_ENA_CLR 0x7fffffff
#define USB_HCSPLT0_SPLT_ENA_MSB 31
#define USB_HCSPLT0_SPLT_ENA_LSB 31
#define USB_HCSPLT0_SPLT_ENA_RESET 0x0
#define USB_HCSPLT0_COMP_SPLT_BITS 16:16
#define USB_HCSPLT0_COMP_SPLT_SET 0x00010000
#define USB_HCSPLT0_COMP_SPLT_CLR 0xfffeffff
#define USB_HCSPLT0_COMP_SPLT_MSB 16
#define USB_HCSPLT0_COMP_SPLT_LSB 16
#define USB_HCSPLT0_COMP_SPLT_RESET 0x0
#define USB_HCSPLT0_XACT_POS_BITS 15:14
#define USB_HCSPLT0_XACT_POS_SET 0x0000c000
#define USB_HCSPLT0_XACT_POS_CLR 0xffff3fff
#define USB_HCSPLT0_XACT_POS_MSB 15
#define USB_HCSPLT0_XACT_POS_LSB 14
#define USB_HCSPLT0_XACT_POS_RESET 0x0
#define USB_HCSPLT0_HUB_ADDR_BITS 13:7
#define USB_HCSPLT0_HUB_ADDR_SET 0x00003f80
#define USB_HCSPLT0_HUB_ADDR_CLR 0xffffc07f
#define USB_HCSPLT0_HUB_ADDR_MSB 13
#define USB_HCSPLT0_HUB_ADDR_LSB 7
#define USB_HCSPLT0_HUB_ADDR_RESET 0x0
#define USB_HCSPLT0_PRT_ADDR_BITS 6:0
#define USB_HCSPLT0_PRT_ADDR_SET 0x0000007f
#define USB_HCSPLT0_PRT_ADDR_CLR 0xffffff80
#define USB_HCSPLT0_PRT_ADDR_MSB 6
#define USB_HCSPLT0_PRT_ADDR_LSB 0
#define USB_HCSPLT0_PRT_ADDR_RESET 0x0
#define USB_HCINT0 HW_REGISTER_RW( 0x7e980508 )
#define USB_HCINT0_MASK 0xffffffff
#define USB_HCINT0_WIDTH 32
#define USB_HCINT0_DATA_TGL_ERR_BITS 10:10
#define USB_HCINT0_DATA_TGL_ERR_SET 0x00000400
#define USB_HCINT0_DATA_TGL_ERR_CLR 0xfffffbff
#define USB_HCINT0_DATA_TGL_ERR_MSB 10
#define USB_HCINT0_DATA_TGL_ERR_LSB 10
#define USB_HCINT0_DATA_TGL_ERR_RESET 0x0
#define USB_HCINT0_FRM_OVRUN_BITS 9:9
#define USB_HCINT0_FRM_OVRUN_SET 0x00000200
#define USB_HCINT0_FRM_OVRUN_CLR 0xfffffdff
#define USB_HCINT0_FRM_OVRUN_MSB 9
#define USB_HCINT0_FRM_OVRUN_LSB 9
#define USB_HCINT0_FRM_OVRUN_RESET 0x0
#define USB_HCINT0_BBL_ERR_BITS 8:8
#define USB_HCINT0_BBL_ERR_SET 0x00000100
#define USB_HCINT0_BBL_ERR_CLR 0xfffffeff
#define USB_HCINT0_BBL_ERR_MSB 8
#define USB_HCINT0_BBL_ERR_LSB 8
#define USB_HCINT0_BBL_ERR_RESET 0x0
#define USB_HCINT0_XACT_ERR_BITS 7:7
#define USB_HCINT0_XACT_ERR_SET 0x00000080
#define USB_HCINT0_XACT_ERR_CLR 0xffffff7f
#define USB_HCINT0_XACT_ERR_MSB 7
#define USB_HCINT0_XACT_ERR_LSB 7
#define USB_HCINT0_XACT_ERR_RESET 0x0
#define USB_HCINT0_NYET_BITS 6:6
#define USB_HCINT0_NYET_SET 0x00000040
#define USB_HCINT0_NYET_CLR 0xffffffbf
#define USB_HCINT0_NYET_MSB 6
#define USB_HCINT0_NYET_LSB 6
#define USB_HCINT0_NYET_RESET 0x0
#define USB_HCINT0_ACK_BITS 5:5
#define USB_HCINT0_ACK_SET 0x00000020
#define USB_HCINT0_ACK_CLR 0xffffffdf
#define USB_HCINT0_ACK_MSB 5
#define USB_HCINT0_ACK_LSB 5
#define USB_HCINT0_ACK_RESET 0x0
#define USB_HCINT0_NAK_BITS 4:4
#define USB_HCINT0_NAK_SET 0x00000010
#define USB_HCINT0_NAK_CLR 0xffffffef
#define USB_HCINT0_NAK_MSB 4
#define USB_HCINT0_NAK_LSB 4
#define USB_HCINT0_NAK_RESET 0x0
#define USB_HCINT0_STALL_BITS 3:3
#define USB_HCINT0_STALL_SET 0x00000008
#define USB_HCINT0_STALL_CLR 0xfffffff7
#define USB_HCINT0_STALL_MSB 3
#define USB_HCINT0_STALL_LSB 3
#define USB_HCINT0_STALL_RESET 0x0
#define USB_HCINT0_AHB_ERR_BITS 2:2
#define USB_HCINT0_AHB_ERR_SET 0x00000004
#define USB_HCINT0_AHB_ERR_CLR 0xfffffffb
#define USB_HCINT0_AHB_ERR_MSB 2
#define USB_HCINT0_AHB_ERR_LSB 2
#define USB_HCINT0_AHB_ERR_RESET 0x0
#define USB_HCINT0_CH_HLTD_BITS 1:1
#define USB_HCINT0_CH_HLTD_SET 0x00000002
#define USB_HCINT0_CH_HLTD_CLR 0xfffffffd
#define USB_HCINT0_CH_HLTD_MSB 1
#define USB_HCINT0_CH_HLTD_LSB 1
#define USB_HCINT0_CH_HLTD_RESET 0x0
#define USB_HCINT0_XFER_COMPL_BITS 0:0
#define USB_HCINT0_XFER_COMPL_SET 0x00000001
#define USB_HCINT0_XFER_COMPL_CLR 0xfffffffe
#define USB_HCINT0_XFER_COMPL_MSB 0
#define USB_HCINT0_XFER_COMPL_LSB 0
#define USB_HCINT0_XFER_COMPL_RESET 0x0
#define USB_HCINTMSK0 HW_REGISTER_RW( 0x7e98050c )
#define USB_HCINTMSK0_MASK 0xffffffff
#define USB_HCINTMSK0_WIDTH 32
#define USB_HCTSIZ0 HW_REGISTER_RW( 0x7e980510 )
#define USB_HCTSIZ0_MASK 0xffffffff
#define USB_HCTSIZ0_WIDTH 32
#define USB_HCTSIZ0_DO_PNG_BITS 31:31
#define USB_HCTSIZ0_DO_PNG_SET 0x80000000
#define USB_HCTSIZ0_DO_PNG_CLR 0x7fffffff
#define USB_HCTSIZ0_DO_PNG_MSB 31
#define USB_HCTSIZ0_DO_PNG_LSB 31
#define USB_HCTSIZ0_DO_PNG_RESET 0x0
#define USB_HCTSIZ0_PID_BITS 30:29
#define USB_HCTSIZ0_PID_SET 0x60000000
#define USB_HCTSIZ0_PID_CLR 0x9fffffff
#define USB_HCTSIZ0_PID_MSB 30
#define USB_HCTSIZ0_PID_LSB 29
#define USB_HCTSIZ0_PID_RESET 0x0
#define USB_HCTSIZ0_PKT_CNT_BITS 28:19
#define USB_HCTSIZ0_PKT_CNT_SET 0x1ff80000
#define USB_HCTSIZ0_PKT_CNT_CLR 0xe007ffff
#define USB_HCTSIZ0_PKT_CNT_MSB 28
#define USB_HCTSIZ0_PKT_CNT_LSB 19
#define USB_HCTSIZ0_PKT_CNT_RESET 0x0
#define USB_HCTSIZ0_XFER_SIZE_BITS 18:0
#define USB_HCTSIZ0_XFER_SIZE_SET 0x0007ffff
#define USB_HCTSIZ0_XFER_SIZE_CLR 0xfff80000
#define USB_HCTSIZ0_XFER_SIZE_MSB 18
#define USB_HCTSIZ0_XFER_SIZE_LSB 0
#define USB_HCTSIZ0_XFER_SIZE_RESET 0x0
#define USB_HCDMA0 HW_REGISTER_RW( 0x7e980514 )
#define USB_HCDMA0_MASK 0xffffffff
#define USB_HCDMA0_WIDTH 32
#define USB_HCCHAR1 HW_REGISTER_RW( 0x7e980520 )
#define USB_HCCHAR1_MASK 0xffffffff
#define USB_HCCHAR1_WIDTH 32
#define USB_HCSPLT1 HW_REGISTER_RW( 0x7e980524 )
#define USB_HCSPLT1_MASK 0xffffffff
#define USB_HCSPLT1_WIDTH 32
#define USB_HCINT1 HW_REGISTER_RW( 0x7e980528 )
#define USB_HCINT1_MASK 0xffffffff
#define USB_HCINT1_WIDTH 32
#define USB_HCINTMSK1 HW_REGISTER_RW( 0x7e98052c )
#define USB_HCINTMSK1_MASK 0xffffffff
#define USB_HCINTMSK1_WIDTH 32
#define USB_HCTSIZ1 HW_REGISTER_RW( 0x7e980530 )
#define USB_HCTSIZ1_MASK 0xffffffff
#define USB_HCTSIZ1_WIDTH 32
#define USB_HCDMA1 HW_REGISTER_RW( 0x7e980534 )
#define USB_HCDMA1_MASK 0xffffffff
#define USB_HCDMA1_WIDTH 32
#define USB_HCCHAR2 HW_REGISTER_RW( 0x7e980540 )
#define USB_HCCHAR2_MASK 0xffffffff
#define USB_HCCHAR2_WIDTH 32
#define USB_HCSPLT2 HW_REGISTER_RW( 0x7e980544 )
#define USB_HCSPLT2_MASK 0xffffffff
#define USB_HCSPLT2_WIDTH 32
#define USB_HCINT2 HW_REGISTER_RW( 0x7e980548 )
#define USB_HCINT2_MASK 0xffffffff
#define USB_HCINT2_WIDTH 32
#define USB_HCINTMSK2 HW_REGISTER_RW( 0x7e98054c )
#define USB_HCINTMSK2_MASK 0xffffffff
#define USB_HCINTMSK2_WIDTH 32
#define USB_HCTSIZ2 HW_REGISTER_RW( 0x7e980550 )
#define USB_HCTSIZ2_MASK 0xffffffff
#define USB_HCTSIZ2_WIDTH 32
#define USB_HCDMA2 HW_REGISTER_RW( 0x7e980554 )
#define USB_HCDMA2_MASK 0xffffffff
#define USB_HCDMA2_WIDTH 32
#define USB_HCCHAR3 HW_REGISTER_RW( 0x7e980560 )
#define USB_HCCHAR3_MASK 0xffffffff
#define USB_HCCHAR3_WIDTH 32
#define USB_HCSPLT3 HW_REGISTER_RW( 0x7e980564 )
#define USB_HCSPLT3_MASK 0xffffffff
#define USB_HCSPLT3_WIDTH 32
#define USB_HCINT3 HW_REGISTER_RW( 0x7e980568 )
#define USB_HCINT3_MASK 0xffffffff
#define USB_HCINT3_WIDTH 32
#define USB_HCINTMSK3 HW_REGISTER_RW( 0x7e98056c )
#define USB_HCINTMSK3_MASK 0xffffffff
#define USB_HCINTMSK3_WIDTH 32
#define USB_HCTSIZ3 HW_REGISTER_RW( 0x7e980570 )
#define USB_HCTSIZ3_MASK 0xffffffff
#define USB_HCTSIZ3_WIDTH 32
#define USB_HCDMA3 HW_REGISTER_RW( 0x7e980574 )
#define USB_HCDMA3_MASK 0xffffffff
#define USB_HCDMA3_WIDTH 32
#define USB_HCCHAR4 HW_REGISTER_RW( 0x7e980580 )
#define USB_HCCHAR4_MASK 0xffffffff
#define USB_HCCHAR4_WIDTH 32
#define USB_HCSPLT4 HW_REGISTER_RW( 0x7e980584 )
#define USB_HCSPLT4_MASK 0xffffffff
#define USB_HCSPLT4_WIDTH 32
#define USB_HCINT4 HW_REGISTER_RW( 0x7e980588 )
#define USB_HCINT4_MASK 0xffffffff
#define USB_HCINT4_WIDTH 32
#define USB_HCINTMSK4 HW_REGISTER_RW( 0x7e98058c )
#define USB_HCINTMSK4_MASK 0xffffffff
#define USB_HCINTMSK4_WIDTH 32
#define USB_HCTSIZ4 HW_REGISTER_RW( 0x7e980590 )
#define USB_HCTSIZ4_MASK 0xffffffff
#define USB_HCTSIZ4_WIDTH 32
#define USB_HCDMA4 HW_REGISTER_RW( 0x7e980594 )
#define USB_HCDMA4_MASK 0xffffffff
#define USB_HCDMA4_WIDTH 32
#define USB_HCCHAR5 HW_REGISTER_RW( 0x7e9805a0 )
#define USB_HCCHAR5_MASK 0xffffffff
#define USB_HCCHAR5_WIDTH 32
#define USB_HCSPLT5 HW_REGISTER_RW( 0x7e9805a4 )
#define USB_HCSPLT5_MASK 0xffffffff
#define USB_HCSPLT5_WIDTH 32
#define USB_HCINT5 HW_REGISTER_RW( 0x7e9805a8 )
#define USB_HCINT5_MASK 0xffffffff
#define USB_HCINT5_WIDTH 32
#define USB_HCINTMSK5 HW_REGISTER_RW( 0x7e9805ac )
#define USB_HCINTMSK5_MASK 0xffffffff
#define USB_HCINTMSK5_WIDTH 32
#define USB_HCTSIZ5 HW_REGISTER_RW( 0x7e9805b0 )
#define USB_HCTSIZ5_MASK 0xffffffff
#define USB_HCTSIZ5_WIDTH 32
#define USB_HCDMA5 HW_REGISTER_RW( 0x7e9805b4 )
#define USB_HCDMA5_MASK 0xffffffff
#define USB_HCDMA5_WIDTH 32
#define USB_HCCHAR6 HW_REGISTER_RW( 0x7e9805c0 )
#define USB_HCCHAR6_MASK 0xffffffff
#define USB_HCCHAR6_WIDTH 32
#define USB_HCSPLT6 HW_REGISTER_RW( 0x7e9805c4 )
#define USB_HCSPLT6_MASK 0xffffffff
#define USB_HCSPLT6_WIDTH 32
#define USB_HCINT6 HW_REGISTER_RW( 0x7e9805c8 )
#define USB_HCINT6_MASK 0xffffffff
#define USB_HCINT6_WIDTH 32
#define USB_HCINTMSK6 HW_REGISTER_RW( 0x7e9805cc )
#define USB_HCINTMSK6_MASK 0xffffffff
#define USB_HCINTMSK6_WIDTH 32
#define USB_HCTSIZ6 HW_REGISTER_RW( 0x7e9805d0 )
#define USB_HCTSIZ6_MASK 0xffffffff
#define USB_HCTSIZ6_WIDTH 32
#define USB_HCDMA6 HW_REGISTER_RW( 0x7e9805d4 )
#define USB_HCDMA6_MASK 0xffffffff
#define USB_HCDMA6_WIDTH 32
#define USB_HCCHAR7 HW_REGISTER_RW( 0x7e9805e0 )
#define USB_HCCHAR7_MASK 0xffffffff
#define USB_HCCHAR7_WIDTH 32
#define USB_HCSPLT7 HW_REGISTER_RW( 0x7e9805e4 )
#define USB_HCSPLT7_MASK 0xffffffff
#define USB_HCSPLT7_WIDTH 32
#define USB_HCINT7 HW_REGISTER_RW( 0x7e9805e8 )
#define USB_HCINT7_MASK 0xffffffff
#define USB_HCINT7_WIDTH 32
#define USB_HCINTMSK7 HW_REGISTER_RW( 0x7e9805ec )
#define USB_HCINTMSK7_MASK 0xffffffff
#define USB_HCINTMSK7_WIDTH 32
#define USB_HCTSIZ7 HW_REGISTER_RW( 0x7e9805f0 )
#define USB_HCTSIZ7_MASK 0xffffffff
#define USB_HCTSIZ7_WIDTH 32
#define USB_HCDMA7 HW_REGISTER_RW( 0x7e9805f4 )
#define USB_HCDMA7_MASK 0xffffffff
#define USB_HCDMA7_WIDTH 32
#define USB_DCFG HW_REGISTER_RW( 0x7e980800 )
#define USB_DCFG_MASK 0x03fc1ff7
#define USB_DCFG_WIDTH 26
#define USB_DCFG_PER_SCH_INTV_BITS 25:24
#define USB_DCFG_PER_SCH_INTV_SET 0x03000000
#define USB_DCFG_PER_SCH_INTV_CLR 0xfcffffff
#define USB_DCFG_PER_SCH_INTV_MSB 25
#define USB_DCFG_PER_SCH_INTV_LSB 24
#define USB_DCFG_PER_SCH_INTV_RESET 0x0
#define USB_DCFG_DESC_DMA_BITS 23:23
#define USB_DCFG_DESC_DMA_SET 0x00800000
#define USB_DCFG_DESC_DMA_CLR 0xff7fffff
#define USB_DCFG_DESC_DMA_MSB 23
#define USB_DCFG_DESC_DMA_LSB 23
#define USB_DCFG_DESC_DMA_RESET 0x0
#define USB_DCFG_EP_MIS_CNT_BITS 22:18
#define USB_DCFG_EP_MIS_CNT_SET 0x007c0000
#define USB_DCFG_EP_MIS_CNT_CLR 0xff83ffff
#define USB_DCFG_EP_MIS_CNT_MSB 22
#define USB_DCFG_EP_MIS_CNT_LSB 18
#define USB_DCFG_EP_MIS_CNT_RESET 0x0
#define USB_DCFG_PER_FR_INT_BITS 12:11
#define USB_DCFG_PER_FR_INT_SET 0x00001800
#define USB_DCFG_PER_FR_INT_CLR 0xffffe7ff
#define USB_DCFG_PER_FR_INT_MSB 12
#define USB_DCFG_PER_FR_INT_LSB 11
#define USB_DCFG_PER_FR_INT_RESET 0x0
#define USB_DCFG_DEV_ADDR_BITS 10:4
#define USB_DCFG_DEV_ADDR_SET 0x000007f0
#define USB_DCFG_DEV_ADDR_CLR 0xfffff80f
#define USB_DCFG_DEV_ADDR_MSB 10
#define USB_DCFG_DEV_ADDR_LSB 4
#define USB_DCFG_DEV_ADDR_RESET 0x0
#define USB_DCFG_NZ_STS_OUT_HSHK_BITS 2:2
#define USB_DCFG_NZ_STS_OUT_HSHK_SET 0x00000004
#define USB_DCFG_NZ_STS_OUT_HSHK_CLR 0xfffffffb
#define USB_DCFG_NZ_STS_OUT_HSHK_MSB 2
#define USB_DCFG_NZ_STS_OUT_HSHK_LSB 2
#define USB_DCFG_NZ_STS_OUT_HSHK_RESET 0x0
#define USB_DCFG_DEV_SPD_BITS 1:0
#define USB_DCFG_DEV_SPD_SET 0x00000003
#define USB_DCFG_DEV_SPD_CLR 0xfffffffc
#define USB_DCFG_DEV_SPD_MSB 1
#define USB_DCFG_DEV_SPD_LSB 0
#define USB_DCFG_DEV_SPD_RESET 0x0
#define USB_DCTL HW_REGISTER_RW( 0x7e980804 )
#define USB_DCTL_MASK 0x0000efff
#define USB_DCTL_WIDTH 16
#define USB_DCTL_IGN_FRM_NUM_BITS 15:15
#define USB_DCTL_IGN_FRM_NUM_SET 0x00008000
#define USB_DCTL_IGN_FRM_NUM_CLR 0xffff7fff
#define USB_DCTL_IGN_FRM_NUM_MSB 15
#define USB_DCTL_IGN_FRM_NUM_LSB 15
#define USB_DCTL_IGN_FRM_NUM_RESET 0x0
#define USB_DCTL_GMC_BITS 14:13
#define USB_DCTL_GMC_SET 0x00006000
#define USB_DCTL_GMC_CLR 0xffff9fff
#define USB_DCTL_GMC_MSB 14
#define USB_DCTL_GMC_LSB 13
#define USB_DCTL_GMC_RESET 0x0
#define USB_DCTL_PWRON_PRG_DONE_BITS 11:11
#define USB_DCTL_PWRON_PRG_DONE_SET 0x00000800
#define USB_DCTL_PWRON_PRG_DONE_CLR 0xfffff7ff
#define USB_DCTL_PWRON_PRG_DONE_MSB 11
#define USB_DCTL_PWRON_PRG_DONE_LSB 11
#define USB_DCTL_PWRON_PRG_DONE_RESET 0x0
#define USB_DCTL_CGOUT_NAK_BITS 10:10
#define USB_DCTL_CGOUT_NAK_SET 0x00000400
#define USB_DCTL_CGOUT_NAK_CLR 0xfffffbff
#define USB_DCTL_CGOUT_NAK_MSB 10
#define USB_DCTL_CGOUT_NAK_LSB 10
#define USB_DCTL_CGOUT_NAK_RESET 0x0
#define USB_DCTL_SGOUT_NAK_BITS 9:9
#define USB_DCTL_SGOUT_NAK_SET 0x00000200
#define USB_DCTL_SGOUT_NAK_CLR 0xfffffdff
#define USB_DCTL_SGOUT_NAK_MSB 9
#define USB_DCTL_SGOUT_NAK_LSB 9
#define USB_DCTL_SGOUT_NAK_RESET 0x0
#define USB_DCTL_CGNP_IN_NAK_BITS 8:8
#define USB_DCTL_CGNP_IN_NAK_SET 0x00000100
#define USB_DCTL_CGNP_IN_NAK_CLR 0xfffffeff
#define USB_DCTL_CGNP_IN_NAK_MSB 8
#define USB_DCTL_CGNP_IN_NAK_LSB 8
#define USB_DCTL_CGNP_IN_NAK_RESET 0x0
#define USB_DCTL_SGNP_IN_NAK_BITS 7:7
#define USB_DCTL_SGNP_IN_NAK_SET 0x00000080
#define USB_DCTL_SGNP_IN_NAK_CLR 0xffffff7f
#define USB_DCTL_SGNP_IN_NAK_MSB 7
#define USB_DCTL_SGNP_IN_NAK_LSB 7
#define USB_DCTL_SGNP_IN_NAK_RESET 0x0
#define USB_DCTL_TST_CTL_BITS 6:4
#define USB_DCTL_TST_CTL_SET 0x00000070
#define USB_DCTL_TST_CTL_CLR 0xffffff8f
#define USB_DCTL_TST_CTL_MSB 6
#define USB_DCTL_TST_CTL_LSB 4
#define USB_DCTL_TST_CTL_RESET 0x0
#define USB_DCTL_GOUT_NAK_STS_BITS 3:3
#define USB_DCTL_GOUT_NAK_STS_SET 0x00000008
#define USB_DCTL_GOUT_NAK_STS_CLR 0xfffffff7
#define USB_DCTL_GOUT_NAK_STS_MSB 3
#define USB_DCTL_GOUT_NAK_STS_LSB 3
#define USB_DCTL_GOUT_NAK_STS_RESET 0x0
#define USB_DCTL_GNP_IN_NAK_STS_BITS 2:2
#define USB_DCTL_GNP_IN_NAK_STS_SET 0x00000004
#define USB_DCTL_GNP_IN_NAK_STS_CLR 0xfffffffb
#define USB_DCTL_GNP_IN_NAK_STS_MSB 2
#define USB_DCTL_GNP_IN_NAK_STS_LSB 2
#define USB_DCTL_GNP_IN_NAK_STS_RESET 0x0
#define USB_DCTL_SFT_DISCON_BITS 1:1
#define USB_DCTL_SFT_DISCON_SET 0x00000002
#define USB_DCTL_SFT_DISCON_CLR 0xfffffffd
#define USB_DCTL_SFT_DISCON_MSB 1
#define USB_DCTL_SFT_DISCON_LSB 1
#define USB_DCTL_SFT_DISCON_RESET 0x0
#define USB_DCTL_RMT_WKUP_SIG_BITS 0:0
#define USB_DCTL_RMT_WKUP_SIG_SET 0x00000001
#define USB_DCTL_RMT_WKUP_SIG_CLR 0xfffffffe
#define USB_DCTL_RMT_WKUP_SIG_MSB 0
#define USB_DCTL_RMT_WKUP_SIG_LSB 0
#define USB_DCTL_RMT_WKUP_SIG_RESET 0x0
#define USB_DSTS HW_REGISTER_RW( 0x7e980808 )
#define USB_DSTS_MASK 0x003fff0f
#define USB_DSTS_WIDTH 22
#define USB_DSTS_SOF_FN_BITS 21:8
#define USB_DSTS_SOF_FN_SET 0x003fff00
#define USB_DSTS_SOF_FN_CLR 0xffc000ff
#define USB_DSTS_SOF_FN_MSB 21
#define USB_DSTS_SOF_FN_LSB 8
#define USB_DSTS_SOF_FN_RESET 0x0
#define USB_DSTS_ERRTIC_ERR_BITS 3:3
#define USB_DSTS_ERRTIC_ERR_SET 0x00000008
#define USB_DSTS_ERRTIC_ERR_CLR 0xfffffff7
#define USB_DSTS_ERRTIC_ERR_MSB 3
#define USB_DSTS_ERRTIC_ERR_LSB 3
#define USB_DSTS_ERRTIC_ERR_RESET 0x0
#define USB_DSTS_ENUM_SPD_BITS 2:1
#define USB_DSTS_ENUM_SPD_SET 0x00000006
#define USB_DSTS_ENUM_SPD_CLR 0xfffffff9
#define USB_DSTS_ENUM_SPD_MSB 2
#define USB_DSTS_ENUM_SPD_LSB 1
#define USB_DSTS_ENUM_SPD_RESET 0x0
#define USB_DSTS_SUSP_STS_BITS 0:0
#define USB_DSTS_SUSP_STS_SET 0x00000001
#define USB_DSTS_SUSP_STS_CLR 0xfffffffe
#define USB_DSTS_SUSP_STS_MSB 0
#define USB_DSTS_SUSP_STS_LSB 0
#define USB_DSTS_SUSP_STS_RESET 0x0
#define USB_DIEPMSK HW_REGISTER_RW( 0x7e980810 )
#define USB_DIEPMSK_MASK 0xffffffff
#define USB_DIEPMSK_WIDTH 32
#define USB_DOEPMSK HW_REGISTER_RW( 0x7e980814 )
#define USB_DOEPMSK_MASK 0xffffffff
#define USB_DOEPMSK_WIDTH 32
#define USB_DAINT HW_REGISTER_RW( 0x7e980818 )
#define USB_DAINT_MASK 0xffffffff
#define USB_DAINT_WIDTH 32
#define USB_DAINT_OUT_EP_INT_BITS 31:16
#define USB_DAINT_OUT_EP_INT_SET 0xffff0000
#define USB_DAINT_OUT_EP_INT_CLR 0x0000ffff
#define USB_DAINT_OUT_EP_INT_MSB 31
#define USB_DAINT_OUT_EP_INT_LSB 16
#define USB_DAINT_OUT_EP_INT_RESET 0x0
#define USB_DAINT_IN_EP_INT_BITS 15:0
#define USB_DAINT_IN_EP_INT_SET 0x0000ffff
#define USB_DAINT_IN_EP_INT_CLR 0xffff0000
#define USB_DAINT_IN_EP_INT_MSB 15
#define USB_DAINT_IN_EP_INT_LSB 0
#define USB_DAINT_IN_EP_INT_RESET 0x0
#define USB_DAINTMSK HW_REGISTER_RW( 0x7e98081c )
#define USB_DAINTMSK_MASK 0xffffffff
#define USB_DAINTMSK_WIDTH 32
#define USB_DTKNQR1 HW_REGISTER_RW( 0x7e980820 )
#define USB_DTKNQR1_MASK 0xffffffff
#define USB_DTKNQR1_WIDTH 32
#define USB_DTKNQR2 HW_REGISTER_RW( 0x7e980824 )
#define USB_DTKNQR2_MASK 0xffffffff
#define USB_DTKNQR2_WIDTH 32
#define USB_DVBUSDIS HW_REGISTER_RW( 0x7e980828 )
#define USB_DVBUSDIS_MASK 0x0000ffff
#define USB_DVBUSDIS_WIDTH 16
#define USB_DVBUSPULSE HW_REGISTER_RW( 0x7e98082c )
#define USB_DVBUSPULSE_MASK 0x00000fff
#define USB_DVBUSPULSE_WIDTH 12
#define USB_DVBUSPULSE_PULSE_BITS 11:0
#define USB_DVBUSPULSE_PULSE_SET 0x00000fff
#define USB_DVBUSPULSE_PULSE_CLR 0xfffff000
#define USB_DVBUSPULSE_PULSE_MSB 11
#define USB_DVBUSPULSE_PULSE_LSB 0
#define USB_DVBUSPULSE_PULSE_RESET 0x0
#define USB_DTKNQR3 HW_REGISTER_RW( 0x7e980830 )
#define USB_DTKNQR3_MASK 0xffffffff
#define USB_DTKNQR3_WIDTH 32
#define USB_DTKNQR4 HW_REGISTER_RW( 0x7e980834 )
#define USB_DTKNQR4_MASK 0xffffffff
#define USB_DTKNQR4_WIDTH 32
#define USB_DTHRCTL HW_REGISTER_RW( 0x7e980830 )
#define USB_DTHRCTL_MASK 0x0fff0fff
#define USB_DTHRCTL_WIDTH 28
#define USB_DTHRCTL_ARB_PRK_EN_BITS 27:27
#define USB_DTHRCTL_ARB_PRK_EN_SET 0x08000000
#define USB_DTHRCTL_ARB_PRK_EN_CLR 0xf7ffffff
#define USB_DTHRCTL_ARB_PRK_EN_MSB 27
#define USB_DTHRCTL_ARB_PRK_EN_LSB 27
#define USB_DTHRCTL_ARB_PRK_EN_RESET 0x0
#define USB_DTHRCTL_RX_THR_LEN_BITS 26:17
#define USB_DTHRCTL_RX_THR_LEN_SET 0x07fe0000
#define USB_DTHRCTL_RX_THR_LEN_CLR 0xf801ffff
#define USB_DTHRCTL_RX_THR_LEN_MSB 26
#define USB_DTHRCTL_RX_THR_LEN_LSB 17
#define USB_DTHRCTL_RX_THR_LEN_RESET 0x0
#define USB_DTHRCTL_RX_THR_EN_BITS 16:16
#define USB_DTHRCTL_RX_THR_EN_SET 0x00010000
#define USB_DTHRCTL_RX_THR_EN_CLR 0xfffeffff
#define USB_DTHRCTL_RX_THR_EN_MSB 16
#define USB_DTHRCTL_RX_THR_EN_LSB 16
#define USB_DTHRCTL_RX_THR_EN_RESET 0x0
#define USB_DTHRCTL_TX_THR_LEN_BITS 10:2
#define USB_DTHRCTL_TX_THR_LEN_SET 0x000007fc
#define USB_DTHRCTL_TX_THR_LEN_CLR 0xfffff803
#define USB_DTHRCTL_TX_THR_LEN_MSB 10
#define USB_DTHRCTL_TX_THR_LEN_LSB 2
#define USB_DTHRCTL_TX_THR_LEN_RESET 0x0
#define USB_DTHRCTL_ISO_THR_EN_BITS 1:1
#define USB_DTHRCTL_ISO_THR_EN_SET 0x00000002
#define USB_DTHRCTL_ISO_THR_EN_CLR 0xfffffffd
#define USB_DTHRCTL_ISO_THR_EN_MSB 1
#define USB_DTHRCTL_ISO_THR_EN_LSB 1
#define USB_DTHRCTL_ISO_THR_EN_RESET 0x0
#define USB_DTHRCTL_NON_ISO_THR_EN_BITS 0:0
#define USB_DTHRCTL_NON_ISO_THR_EN_SET 0x00000001
#define USB_DTHRCTL_NON_ISO_THR_EN_CLR 0xfffffffe
#define USB_DTHRCTL_NON_ISO_THR_EN_MSB 0
#define USB_DTHRCTL_NON_ISO_THR_EN_LSB 0
#define USB_DTHRCTL_NON_ISO_THR_EN_RESET 0x0
#define USB_DIEPEMPMSK HW_REGISTER_RW( 0x7e980834 )
#define USB_DIEPEMPMSK_MASK 0x0000ffff
#define USB_DIEPEMPMSK_WIDTH 16
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_BITS 15:0
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_SET 0x0000ffff
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_CLR 0xffff0000
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_MSB 15
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_LSB 0
#define USB_DIEPEMPMSK_EP_TXF_EMP_MSK_RESET 0x0
#define USB_DIEPCTL0 HW_REGISTER_RW( 0x7e980900 )
#define USB_DIEPCTL0_MASK 0xffffffff
#define USB_DIEPCTL0_WIDTH 32
#define USB_DIEPCTL0_ENA_BITS 31:31
#define USB_DIEPCTL0_ENA_SET 0x80000000
#define USB_DIEPCTL0_ENA_CLR 0x7fffffff
#define USB_DIEPCTL0_ENA_MSB 31
#define USB_DIEPCTL0_ENA_LSB 31
#define USB_DIEPCTL0_ENA_RESET 0x0
#define USB_DIEPCTL0_DIS_BITS 30:30
#define USB_DIEPCTL0_DIS_SET 0x40000000
#define USB_DIEPCTL0_DIS_CLR 0xbfffffff
#define USB_DIEPCTL0_DIS_MSB 30
#define USB_DIEPCTL0_DIS_LSB 30
#define USB_DIEPCTL0_DIS_RESET 0x0
#define USB_DIEPCTL0_SET_D1_PID_BITS 29:29
#define USB_DIEPCTL0_SET_D1_PID_SET 0x20000000
#define USB_DIEPCTL0_SET_D1_PID_CLR 0xdfffffff
#define USB_DIEPCTL0_SET_D1_PID_MSB 29
#define USB_DIEPCTL0_SET_D1_PID_LSB 29
#define USB_DIEPCTL0_SET_D1_PID_RESET 0x0
#define USB_DIEPCTL0_SET_ODD_FR_BITS 29:29
#define USB_DIEPCTL0_SET_ODD_FR_SET 0x20000000
#define USB_DIEPCTL0_SET_ODD_FR_CLR 0xdfffffff
#define USB_DIEPCTL0_SET_ODD_FR_MSB 29
#define USB_DIEPCTL0_SET_ODD_FR_LSB 29
#define USB_DIEPCTL0_SET_ODD_FR_RESET 0x0
#define USB_DIEPCTL0_SET_D0_PID_BITS 28:28
#define USB_DIEPCTL0_SET_D0_PID_SET 0x10000000
#define USB_DIEPCTL0_SET_D0_PID_CLR 0xefffffff
#define USB_DIEPCTL0_SET_D0_PID_MSB 28
#define USB_DIEPCTL0_SET_D0_PID_LSB 28
#define USB_DIEPCTL0_SET_D0_PID_RESET 0x0
#define USB_DIEPCTL0_SET_EVEN_FR_BITS 28:28
#define USB_DIEPCTL0_SET_EVEN_FR_SET 0x10000000
#define USB_DIEPCTL0_SET_EVEN_FR_CLR 0xefffffff
#define USB_DIEPCTL0_SET_EVEN_FR_MSB 28
#define USB_DIEPCTL0_SET_EVEN_FR_LSB 28
#define USB_DIEPCTL0_SET_EVEN_FR_RESET 0x0
#define USB_DIEPCTL0_SNAK_BITS 27:27
#define USB_DIEPCTL0_SNAK_SET 0x08000000
#define USB_DIEPCTL0_SNAK_CLR 0xf7ffffff
#define USB_DIEPCTL0_SNAK_MSB 27
#define USB_DIEPCTL0_SNAK_LSB 27
#define USB_DIEPCTL0_SNAK_RESET 0x0
#define USB_DIEPCTL0_CNAK_BITS 26:26
#define USB_DIEPCTL0_CNAK_SET 0x04000000
#define USB_DIEPCTL0_CNAK_CLR 0xfbffffff
#define USB_DIEPCTL0_CNAK_MSB 26
#define USB_DIEPCTL0_CNAK_LSB 26
#define USB_DIEPCTL0_CNAK_RESET 0x0
#define USB_DIEPCTL0_TXF_NUM_BITS 25:22
#define USB_DIEPCTL0_TXF_NUM_SET 0x03c00000
#define USB_DIEPCTL0_TXF_NUM_CLR 0xfc3fffff
#define USB_DIEPCTL0_TXF_NUM_MSB 25
#define USB_DIEPCTL0_TXF_NUM_LSB 22
#define USB_DIEPCTL0_TXF_NUM_RESET 0x0
#define USB_DIEPCTL0_STALL_BITS 21:21
#define USB_DIEPCTL0_STALL_SET 0x00200000
#define USB_DIEPCTL0_STALL_CLR 0xffdfffff
#define USB_DIEPCTL0_STALL_MSB 21
#define USB_DIEPCTL0_STALL_LSB 21
#define USB_DIEPCTL0_STALL_RESET 0x0
#define USB_DIEPCTL0_SNP_BITS 20:20
#define USB_DIEPCTL0_SNP_SET 0x00100000
#define USB_DIEPCTL0_SNP_CLR 0xffefffff
#define USB_DIEPCTL0_SNP_MSB 20
#define USB_DIEPCTL0_SNP_LSB 20
#define USB_DIEPCTL0_SNP_RESET 0x0
#define USB_DIEPCTL0_TYPE_BITS 19:18
#define USB_DIEPCTL0_TYPE_SET 0x000c0000
#define USB_DIEPCTL0_TYPE_CLR 0xfff3ffff
#define USB_DIEPCTL0_TYPE_MSB 19
#define USB_DIEPCTL0_TYPE_LSB 18
#define USB_DIEPCTL0_TYPE_RESET 0x0
#define USB_DIEPCTL0_NAK_STS_BITS 17:17
#define USB_DIEPCTL0_NAK_STS_SET 0x00020000
#define USB_DIEPCTL0_NAK_STS_CLR 0xfffdffff
#define USB_DIEPCTL0_NAK_STS_MSB 17
#define USB_DIEPCTL0_NAK_STS_LSB 17
#define USB_DIEPCTL0_NAK_STS_RESET 0x0
#define USB_DIEPCTL0_DPID_BITS 16:16
#define USB_DIEPCTL0_DPID_SET 0x00010000
#define USB_DIEPCTL0_DPID_CLR 0xfffeffff
#define USB_DIEPCTL0_DPID_MSB 16
#define USB_DIEPCTL0_DPID_LSB 16
#define USB_DIEPCTL0_DPID_RESET 0x0
#define USB_DIEPCTL0_EO_FR_NUM_BITS 16:16
#define USB_DIEPCTL0_EO_FR_NUM_SET 0x00010000
#define USB_DIEPCTL0_EO_FR_NUM_CLR 0xfffeffff
#define USB_DIEPCTL0_EO_FR_NUM_MSB 16
#define USB_DIEPCTL0_EO_FR_NUM_LSB 16
#define USB_DIEPCTL0_EO_FR_NUM_RESET 0x0
#define USB_DIEPCTL0_USB_ACT_EP_BITS 15:15
#define USB_DIEPCTL0_USB_ACT_EP_SET 0x00008000
#define USB_DIEPCTL0_USB_ACT_EP_CLR 0xffff7fff
#define USB_DIEPCTL0_USB_ACT_EP_MSB 15
#define USB_DIEPCTL0_USB_ACT_EP_LSB 15
#define USB_DIEPCTL0_USB_ACT_EP_RESET 0x0
#define USB_DIEPCTL0_NEXT_EP_BITS 14:11
#define USB_DIEPCTL0_NEXT_EP_SET 0x00007800
#define USB_DIEPCTL0_NEXT_EP_CLR 0xffff87ff
#define USB_DIEPCTL0_NEXT_EP_MSB 14
#define USB_DIEPCTL0_NEXT_EP_LSB 11
#define USB_DIEPCTL0_NEXT_EP_RESET 0x0
#define USB_DIEPCTL0_MPS_BITS 10:0
#define USB_DIEPCTL0_MPS_SET 0x000007ff
#define USB_DIEPCTL0_MPS_CLR 0xfffff800
#define USB_DIEPCTL0_MPS_MSB 10
#define USB_DIEPCTL0_MPS_LSB 0
#define USB_DIEPCTL0_MPS_RESET 0x0
#define USB_DIEPINT0 HW_REGISTER_RW( 0x7e980908 )
#define USB_DIEPINT0_MASK 0xffffffff
#define USB_DIEPINT0_WIDTH 32
#define USB_DIEPINT0_BNA_BITS 9:9
#define USB_DIEPINT0_BNA_SET 0x00000200
#define USB_DIEPINT0_BNA_CLR 0xfffffdff
#define USB_DIEPINT0_BNA_MSB 9
#define USB_DIEPINT0_BNA_LSB 9
#define USB_DIEPINT0_BNA_RESET 0x0
#define USB_DIEPINT0_TX_FIFO_UNDRN_BITS 8:8
#define USB_DIEPINT0_TX_FIFO_UNDRN_SET 0x00000100
#define USB_DIEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
#define USB_DIEPINT0_TX_FIFO_UNDRN_MSB 8
#define USB_DIEPINT0_TX_FIFO_UNDRN_LSB 8
#define USB_DIEPINT0_TX_FIFO_UNDRN_RESET 0x0
#define USB_DIEPINT0_OUT_PKT_ERR_BITS 8:8
#define USB_DIEPINT0_OUT_PKT_ERR_SET 0x00000100
#define USB_DIEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
#define USB_DIEPINT0_OUT_PKT_ERR_MSB 8
#define USB_DIEPINT0_OUT_PKT_ERR_LSB 8
#define USB_DIEPINT0_OUT_PKT_ERR_RESET 0x0
#define USB_DIEPINT0_TXF_EMPTY_BITS 7:7
#define USB_DIEPINT0_TXF_EMPTY_SET 0x00000080
#define USB_DIEPINT0_TXF_EMPTY_CLR 0xffffff7f
#define USB_DIEPINT0_TXF_EMPTY_MSB 7
#define USB_DIEPINT0_TXF_EMPTY_LSB 7
#define USB_DIEPINT0_TXF_EMPTY_RESET 0x0
#define USB_DIEPINT0_IN_EP_NAK_EFF_BITS 6:6
#define USB_DIEPINT0_IN_EP_NAK_EFF_SET 0x00000040
#define USB_DIEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
#define USB_DIEPINT0_IN_EP_NAK_EFF_MSB 6
#define USB_DIEPINT0_IN_EP_NAK_EFF_LSB 6
#define USB_DIEPINT0_IN_EP_NAK_EFF_RESET 0x0
#define USB_DIEPINT0_BACK2BACK_SETUP_BITS 6:6
#define USB_DIEPINT0_BACK2BACK_SETUP_SET 0x00000040
#define USB_DIEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
#define USB_DIEPINT0_BACK2BACK_SETUP_MSB 6
#define USB_DIEPINT0_BACK2BACK_SETUP_LSB 6
#define USB_DIEPINT0_BACK2BACK_SETUP_RESET 0x0
#define USB_DIEPINT0_IN_TKN_EP_MIS_BITS 5:5
#define USB_DIEPINT0_IN_TKN_EP_MIS_SET 0x00000020
#define USB_DIEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
#define USB_DIEPINT0_IN_TKN_EP_MIS_MSB 5
#define USB_DIEPINT0_IN_TKN_EP_MIS_LSB 5
#define USB_DIEPINT0_IN_TKN_EP_MIS_RESET 0x0
#define USB_DIEPINT0_STS_PHSE_RCVD_BITS 5:5
#define USB_DIEPINT0_STS_PHSE_RCVD_SET 0x00000020
#define USB_DIEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
#define USB_DIEPINT0_STS_PHSE_RCVD_MSB 5
#define USB_DIEPINT0_STS_PHSE_RCVD_LSB 5
#define USB_DIEPINT0_STS_PHSE_RCVD_RESET 0x0
#define USB_DIEPINT0_IN_TKN_TXFEMP_BITS 4:4
#define USB_DIEPINT0_IN_TKN_TXFEMP_SET 0x00000010
#define USB_DIEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
#define USB_DIEPINT0_IN_TKN_TXFEMP_MSB 4
#define USB_DIEPINT0_IN_TKN_TXFEMP_LSB 4
#define USB_DIEPINT0_IN_TKN_TXFEMP_RESET 0x0
#define USB_DIEPINT0_OUT_TKN_EP_DIS_BITS 4:4
#define USB_DIEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
#define USB_DIEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
#define USB_DIEPINT0_OUT_TKN_EP_DIS_MSB 4
#define USB_DIEPINT0_OUT_TKN_EP_DIS_LSB 4
#define USB_DIEPINT0_OUT_TKN_EP_DIS_RESET 0x0
#define USB_DIEPINT0_TIMEOUT_BITS 3:3
#define USB_DIEPINT0_TIMEOUT_SET 0x00000008
#define USB_DIEPINT0_TIMEOUT_CLR 0xfffffff7
#define USB_DIEPINT0_TIMEOUT_MSB 3
#define USB_DIEPINT0_TIMEOUT_LSB 3
#define USB_DIEPINT0_TIMEOUT_RESET 0x0
#define USB_DIEPINT0_SETUP_BITS 3:3
#define USB_DIEPINT0_SETUP_SET 0x00000008
#define USB_DIEPINT0_SETUP_CLR 0xfffffff7
#define USB_DIEPINT0_SETUP_MSB 3
#define USB_DIEPINT0_SETUP_LSB 3
#define USB_DIEPINT0_SETUP_RESET 0x0
#define USB_DIEPINT0_AHB_ERR_BITS 2:2
#define USB_DIEPINT0_AHB_ERR_SET 0x00000004
#define USB_DIEPINT0_AHB_ERR_CLR 0xfffffffb
#define USB_DIEPINT0_AHB_ERR_MSB 2
#define USB_DIEPINT0_AHB_ERR_LSB 2
#define USB_DIEPINT0_AHB_ERR_RESET 0x0
#define USB_DIEPINT0_EP_DISBLD_BITS 1:1
#define USB_DIEPINT0_EP_DISBLD_SET 0x00000002
#define USB_DIEPINT0_EP_DISBLD_CLR 0xfffffffd
#define USB_DIEPINT0_EP_DISBLD_MSB 1
#define USB_DIEPINT0_EP_DISBLD_LSB 1
#define USB_DIEPINT0_EP_DISBLD_RESET 0x0
#define USB_DIEPINT0_XFER_COMPL_BITS 0:0
#define USB_DIEPINT0_XFER_COMPL_SET 0x00000001
#define USB_DIEPINT0_XFER_COMPL_CLR 0xfffffffe
#define USB_DIEPINT0_XFER_COMPL_MSB 0
#define USB_DIEPINT0_XFER_COMPL_LSB 0
#define USB_DIEPINT0_XFER_COMPL_RESET 0x0
#define USB_DIEPTSIZ0 HW_REGISTER_RW( 0x7e980910 )
#define USB_DIEPTSIZ0_MASK 0xffffffff
#define USB_DIEPTSIZ0_WIDTH 32
#define USB_DIEPTSIZ0_SUP_CNT_BITS 30:29
#define USB_DIEPTSIZ0_SUP_CNT_SET 0x60000000
#define USB_DIEPTSIZ0_SUP_CNT_CLR 0x9fffffff
#define USB_DIEPTSIZ0_SUP_CNT_MSB 30
#define USB_DIEPTSIZ0_SUP_CNT_LSB 29
#define USB_DIEPTSIZ0_SUP_CNT_RESET 0x0
#define USB_DIEPTSIZ0_RX_DPID_BITS 30:29
#define USB_DIEPTSIZ0_RX_DPID_SET 0x60000000
#define USB_DIEPTSIZ0_RX_DPID_CLR 0x9fffffff
#define USB_DIEPTSIZ0_RX_DPID_MSB 30
#define USB_DIEPTSIZ0_RX_DPID_LSB 29
#define USB_DIEPTSIZ0_RX_DPID_RESET 0x0
#define USB_DIEPTSIZ0_MC_BITS 30:29
#define USB_DIEPTSIZ0_MC_SET 0x60000000
#define USB_DIEPTSIZ0_MC_CLR 0x9fffffff
#define USB_DIEPTSIZ0_MC_MSB 30
#define USB_DIEPTSIZ0_MC_LSB 29
#define USB_DIEPTSIZ0_MC_RESET 0x0
#define USB_DIEPTSIZ0_PKT_CNT_BITS 28:19
#define USB_DIEPTSIZ0_PKT_CNT_SET 0x1ff80000
#define USB_DIEPTSIZ0_PKT_CNT_CLR 0xe007ffff
#define USB_DIEPTSIZ0_PKT_CNT_MSB 28
#define USB_DIEPTSIZ0_PKT_CNT_LSB 19
#define USB_DIEPTSIZ0_PKT_CNT_RESET 0x0
#define USB_DIEPTSIZ0_XFERSIZE_BITS 18:0
#define USB_DIEPTSIZ0_XFERSIZE_SET 0x0007ffff
#define USB_DIEPTSIZ0_XFERSIZE_CLR 0xfff80000
#define USB_DIEPTSIZ0_XFERSIZE_MSB 18
#define USB_DIEPTSIZ0_XFERSIZE_LSB 0
#define USB_DIEPTSIZ0_XFERSIZE_RESET 0x0
#define USB_DIEPDMA0 HW_REGISTER_RW( 0x7e980914 )
#define USB_DIEPDMA0_MASK 0xffffffff
#define USB_DIEPDMA0_WIDTH 32
#define USB_DTXFSTS0 HW_REGISTER_RW( 0x7e980918 )
#define USB_DTXFSTS0_MASK 0xffffffff
#define USB_DTXFSTS0_WIDTH 32
#define USB_DTXFSTS0_SPC_AVAIL_BITS 31:16
#define USB_DTXFSTS0_SPC_AVAIL_SET 0xffff0000
#define USB_DTXFSTS0_SPC_AVAIL_CLR 0x0000ffff
#define USB_DTXFSTS0_SPC_AVAIL_MSB 31
#define USB_DTXFSTS0_SPC_AVAIL_LSB 16
#define USB_DTXFSTS0_SPC_AVAIL_RESET 0x0
#define USB_DIEPDMAB0 HW_REGISTER_RW( 0x7e980918 )
#define USB_DIEPDMAB0_MASK 0xffffffff
#define USB_DIEPDMAB0_WIDTH 32
#define USB_DIEPCTL1 HW_REGISTER_RW( 0x7e980920 )
#define USB_DIEPCTL1_MASK 0xffffffff
#define USB_DIEPCTL1_WIDTH 32
#define USB_DIEPINT1 HW_REGISTER_RW( 0x7e980928 )
#define USB_DIEPINT1_MASK 0xffffffff
#define USB_DIEPINT1_WIDTH 32
#define USB_DIEPTSIZ1 HW_REGISTER_RW( 0x7e980930 )
#define USB_DIEPTSIZ1_MASK 0xffffffff
#define USB_DIEPTSIZ1_WIDTH 32
#define USB_DIEPDMA1 HW_REGISTER_RW( 0x7e980934 )
#define USB_DIEPDMA1_MASK 0xffffffff
#define USB_DIEPDMA1_WIDTH 32
#define USB_DTXFSTS1 HW_REGISTER_RW( 0x7e980938 )
#define USB_DTXFSTS1_MASK 0xffffffff
#define USB_DTXFSTS1_WIDTH 32
#define USB_DIEPDMAB1 HW_REGISTER_RW( 0x7e980938 )
#define USB_DIEPDMAB1_MASK 0xffffffff
#define USB_DIEPDMAB1_WIDTH 32
#define USB_DIEPCTL2 HW_REGISTER_RW( 0x7e980940 )
#define USB_DIEPCTL2_MASK 0xffffffff
#define USB_DIEPCTL2_WIDTH 32
#define USB_DIEPINT2 HW_REGISTER_RW( 0x7e980948 )
#define USB_DIEPINT2_MASK 0xffffffff
#define USB_DIEPINT2_WIDTH 32
#define USB_DIEPTSIZ2 HW_REGISTER_RW( 0x7e980950 )
#define USB_DIEPTSIZ2_MASK 0xffffffff
#define USB_DIEPTSIZ2_WIDTH 32
#define USB_DIEPDMA2 HW_REGISTER_RW( 0x7e980954 )
#define USB_DIEPDMA2_MASK 0xffffffff
#define USB_DIEPDMA2_WIDTH 32
#define USB_DTXFSTS2 HW_REGISTER_RW( 0x7e980958 )
#define USB_DTXFSTS2_MASK 0xffffffff
#define USB_DTXFSTS2_WIDTH 32
#define USB_DIEPDMAB2 HW_REGISTER_RW( 0x7e980958 )
#define USB_DIEPDMAB2_MASK 0xffffffff
#define USB_DIEPDMAB2_WIDTH 32
#define USB_DIEPCTL3 HW_REGISTER_RW( 0x7e980960 )
#define USB_DIEPCTL3_MASK 0xffffffff
#define USB_DIEPCTL3_WIDTH 32
#define USB_DIEPINT3 HW_REGISTER_RW( 0x7e980968 )
#define USB_DIEPINT3_MASK 0xffffffff
#define USB_DIEPINT3_WIDTH 32
#define USB_DIEPTSIZ3 HW_REGISTER_RW( 0x7e980970 )
#define USB_DIEPTSIZ3_MASK 0xffffffff
#define USB_DIEPTSIZ3_WIDTH 32
#define USB_DIEPDMA3 HW_REGISTER_RW( 0x7e980974 )
#define USB_DIEPDMA3_MASK 0xffffffff
#define USB_DIEPDMA3_WIDTH 32
#define USB_DTXFSTS3 HW_REGISTER_RW( 0x7e980978 )
#define USB_DTXFSTS3_MASK 0xffffffff
#define USB_DTXFSTS3_WIDTH 32
#define USB_DIEPDMAB3 HW_REGISTER_RW( 0x7e980978 )
#define USB_DIEPDMAB3_MASK 0xffffffff
#define USB_DIEPDMAB3_WIDTH 32
#define USB_DIEPCTL4 HW_REGISTER_RW( 0x7e980980 )
#define USB_DIEPCTL4_MASK 0xffffffff
#define USB_DIEPCTL4_WIDTH 32
#define USB_DIEPINT4 HW_REGISTER_RW( 0x7e980988 )
#define USB_DIEPINT4_MASK 0xffffffff
#define USB_DIEPINT4_WIDTH 32
#define USB_DIEPTSIZ4 HW_REGISTER_RW( 0x7e980990 )
#define USB_DIEPTSIZ4_MASK 0xffffffff
#define USB_DIEPTSIZ4_WIDTH 32
#define USB_DIEPDMA4 HW_REGISTER_RW( 0x7e980994 )
#define USB_DIEPDMA4_MASK 0xffffffff
#define USB_DIEPDMA4_WIDTH 32
#define USB_DTXFSTS4 HW_REGISTER_RW( 0x7e980998 )
#define USB_DTXFSTS4_MASK 0xffffffff
#define USB_DTXFSTS4_WIDTH 32
#define USB_DIEPDMAB4 HW_REGISTER_RW( 0x7e980998 )
#define USB_DIEPDMAB4_MASK 0xffffffff
#define USB_DIEPDMAB4_WIDTH 32
#define USB_DIEPCTL5 HW_REGISTER_RW( 0x7e9809a0 )
#define USB_DIEPCTL5_MASK 0xffffffff
#define USB_DIEPCTL5_WIDTH 32
#define USB_DIEPINT5 HW_REGISTER_RW( 0x7e9809a8 )
#define USB_DIEPINT5_MASK 0xffffffff
#define USB_DIEPINT5_WIDTH 32
#define USB_DIEPTSIZ5 HW_REGISTER_RW( 0x7e9809b0 )
#define USB_DIEPTSIZ5_MASK 0xffffffff
#define USB_DIEPTSIZ5_WIDTH 32
#define USB_DIEPDMA5 HW_REGISTER_RW( 0x7e9809b4 )
#define USB_DIEPDMA5_MASK 0xffffffff
#define USB_DIEPDMA5_WIDTH 32
#define USB_DTXFSTS5 HW_REGISTER_RW( 0x7e9809b8 )
#define USB_DTXFSTS5_MASK 0xffffffff
#define USB_DTXFSTS5_WIDTH 32
#define USB_DIEPDMAB5 HW_REGISTER_RW( 0x7e9809b8 )
#define USB_DIEPDMAB5_MASK 0xffffffff
#define USB_DIEPDMAB5_WIDTH 32
#define USB_DIEPCTL6 HW_REGISTER_RW( 0x7e9809c0 )
#define USB_DIEPCTL6_MASK 0xffffffff
#define USB_DIEPCTL6_WIDTH 32
#define USB_DIEPINT6 HW_REGISTER_RW( 0x7e9809c8 )
#define USB_DIEPINT6_MASK 0xffffffff
#define USB_DIEPINT6_WIDTH 32
#define USB_DIEPTSIZ6 HW_REGISTER_RW( 0x7e9809d0 )
#define USB_DIEPTSIZ6_MASK 0xffffffff
#define USB_DIEPTSIZ6_WIDTH 32
#define USB_DIEPDMA6 HW_REGISTER_RW( 0x7e9809d4 )
#define USB_DIEPDMA6_MASK 0xffffffff
#define USB_DIEPDMA6_WIDTH 32
#define USB_DTXFSTS6 HW_REGISTER_RW( 0x7e9809d8 )
#define USB_DTXFSTS6_MASK 0xffffffff
#define USB_DTXFSTS6_WIDTH 32
#define USB_DIEPDMAB6 HW_REGISTER_RW( 0x7e9809d8 )
#define USB_DIEPDMAB6_MASK 0xffffffff
#define USB_DIEPDMAB6_WIDTH 32
#define USB_DIEPCTL7 HW_REGISTER_RW( 0x7e9809e0 )
#define USB_DIEPCTL7_MASK 0xffffffff
#define USB_DIEPCTL7_WIDTH 32
#define USB_DIEPINT7 HW_REGISTER_RW( 0x7e9809e8 )
#define USB_DIEPINT7_MASK 0xffffffff
#define USB_DIEPINT7_WIDTH 32
#define USB_DIEPTSIZ7 HW_REGISTER_RW( 0x7e9809f0 )
#define USB_DIEPTSIZ7_MASK 0xffffffff
#define USB_DIEPTSIZ7_WIDTH 32
#define USB_DIEPDMA7 HW_REGISTER_RW( 0x7e9809f4 )
#define USB_DIEPDMA7_MASK 0xffffffff
#define USB_DIEPDMA7_WIDTH 32
#define USB_DTXFSTS7 HW_REGISTER_RW( 0x7e9809f8 )
#define USB_DTXFSTS7_MASK 0xffffffff
#define USB_DTXFSTS7_WIDTH 32
#define USB_DIEPDMAB7 HW_REGISTER_RW( 0x7e9809f8 )
#define USB_DIEPDMAB7_MASK 0xffffffff
#define USB_DIEPDMAB7_WIDTH 32
#define USB_DIEPCTL8 HW_REGISTER_RW( 0x7e980a00 )
#define USB_DIEPCTL8_MASK 0xffffffff
#define USB_DIEPCTL8_WIDTH 32
#define USB_DIEPINT8 HW_REGISTER_RW( 0x7e980a08 )
#define USB_DIEPINT8_MASK 0xffffffff
#define USB_DIEPINT8_WIDTH 32
#define USB_DIEPTSIZ8 HW_REGISTER_RW( 0x7e980a10 )
#define USB_DIEPTSIZ8_MASK 0xffffffff
#define USB_DIEPTSIZ8_WIDTH 32
#define USB_DIEPDMA8 HW_REGISTER_RW( 0x7e980a14 )
#define USB_DIEPDMA8_MASK 0xffffffff
#define USB_DIEPDMA8_WIDTH 32
#define USB_DTXFSTS8 HW_REGISTER_RW( 0x7e980a18 )
#define USB_DTXFSTS8_MASK 0xffffffff
#define USB_DTXFSTS8_WIDTH 32
#define USB_DIEPDMAB8 HW_REGISTER_RW( 0x7e980a18 )
#define USB_DIEPDMAB8_MASK 0xffffffff
#define USB_DIEPDMAB8_WIDTH 32
#define USB_DIEPCTL9 HW_REGISTER_RW( 0x7e980a20 )
#define USB_DIEPCTL9_MASK 0xffffffff
#define USB_DIEPCTL9_WIDTH 32
#define USB_DIEPINT9 HW_REGISTER_RW( 0x7e980a28 )
#define USB_DIEPINT9_MASK 0xffffffff
#define USB_DIEPINT9_WIDTH 32
#define USB_DIEPTSIZ9 HW_REGISTER_RW( 0x7e980a30 )
#define USB_DIEPTSIZ9_MASK 0xffffffff
#define USB_DIEPTSIZ9_WIDTH 32
#define USB_DIEPDMA9 HW_REGISTER_RW( 0x7e980a34 )
#define USB_DIEPDMA9_MASK 0xffffffff
#define USB_DIEPDMA9_WIDTH 32
#define USB_DTXFSTS9 HW_REGISTER_RW( 0x7e980a38 )
#define USB_DTXFSTS9_MASK 0xffffffff
#define USB_DTXFSTS9_WIDTH 32
#define USB_DIEPDMAB9 HW_REGISTER_RW( 0x7e980a38 )
#define USB_DIEPDMAB9_MASK 0xffffffff
#define USB_DIEPDMAB9_WIDTH 32
#define USB_DIEPCTL10 HW_REGISTER_RW( 0x7e980a40 )
#define USB_DIEPCTL10_MASK 0xffffffff
#define USB_DIEPCTL10_WIDTH 32
#define USB_DIEPINT10 HW_REGISTER_RW( 0x7e980a48 )
#define USB_DIEPINT10_MASK 0xffffffff
#define USB_DIEPINT10_WIDTH 32
#define USB_DIEPTSIZ10 HW_REGISTER_RW( 0x7e980a50 )
#define USB_DIEPTSIZ10_MASK 0xffffffff
#define USB_DIEPTSIZ10_WIDTH 32
#define USB_DIEPDMA10 HW_REGISTER_RW( 0x7e980a54 )
#define USB_DIEPDMA10_MASK 0xffffffff
#define USB_DIEPDMA10_WIDTH 32
#define USB_DTXFSTS10 HW_REGISTER_RW( 0x7e980a58 )
#define USB_DTXFSTS10_MASK 0xffffffff
#define USB_DTXFSTS10_WIDTH 32
#define USB_DIEPDMAB10 HW_REGISTER_RW( 0x7e980a58 )
#define USB_DIEPDMAB10_MASK 0xffffffff
#define USB_DIEPDMAB10_WIDTH 32
#define USB_DIEPCTL11 HW_REGISTER_RW( 0x7e980a60 )
#define USB_DIEPCTL11_MASK 0xffffffff
#define USB_DIEPCTL11_WIDTH 32
#define USB_DIEPINT11 HW_REGISTER_RW( 0x7e980a68 )
#define USB_DIEPINT11_MASK 0xffffffff
#define USB_DIEPINT11_WIDTH 32
#define USB_DIEPTSIZ11 HW_REGISTER_RW( 0x7e980a70 )
#define USB_DIEPTSIZ11_MASK 0xffffffff
#define USB_DIEPTSIZ11_WIDTH 32
#define USB_DIEPDMA11 HW_REGISTER_RW( 0x7e980a74 )
#define USB_DIEPDMA11_MASK 0xffffffff
#define USB_DIEPDMA11_WIDTH 32
#define USB_DTXFSTS11 HW_REGISTER_RW( 0x7e980a78 )
#define USB_DTXFSTS11_MASK 0xffffffff
#define USB_DTXFSTS11_WIDTH 32
#define USB_DIEPDMAB11 HW_REGISTER_RW( 0x7e980a78 )
#define USB_DIEPDMAB11_MASK 0xffffffff
#define USB_DIEPDMAB11_WIDTH 32
#define USB_DIEPCTL12 HW_REGISTER_RW( 0x7e980a80 )
#define USB_DIEPCTL12_MASK 0xffffffff
#define USB_DIEPCTL12_WIDTH 32
#define USB_DIEPINT12 HW_REGISTER_RW( 0x7e980a88 )
#define USB_DIEPINT12_MASK 0xffffffff
#define USB_DIEPINT12_WIDTH 32
#define USB_DIEPTSIZ12 HW_REGISTER_RW( 0x7e980a90 )
#define USB_DIEPTSIZ12_MASK 0xffffffff
#define USB_DIEPTSIZ12_WIDTH 32
#define USB_DIEPDMA12 HW_REGISTER_RW( 0x7e980a94 )
#define USB_DIEPDMA12_MASK 0xffffffff
#define USB_DIEPDMA12_WIDTH 32
#define USB_DTXFSTS12 HW_REGISTER_RW( 0x7e980a98 )
#define USB_DTXFSTS12_MASK 0xffffffff
#define USB_DTXFSTS12_WIDTH 32
#define USB_DIEPDMAB12 HW_REGISTER_RW( 0x7e980a98 )
#define USB_DIEPDMAB12_MASK 0xffffffff
#define USB_DIEPDMAB12_WIDTH 32
#define USB_DIEPCTL13 HW_REGISTER_RW( 0x7e980aa0 )
#define USB_DIEPCTL13_MASK 0xffffffff
#define USB_DIEPCTL13_WIDTH 32
#define USB_DIEPINT13 HW_REGISTER_RW( 0x7e980aa8 )
#define USB_DIEPINT13_MASK 0xffffffff
#define USB_DIEPINT13_WIDTH 32
#define USB_DIEPTSIZ13 HW_REGISTER_RW( 0x7e980ab0 )
#define USB_DIEPTSIZ13_MASK 0xffffffff
#define USB_DIEPTSIZ13_WIDTH 32
#define USB_DIEPDMA13 HW_REGISTER_RW( 0x7e980ab4 )
#define USB_DIEPDMA13_MASK 0xffffffff
#define USB_DIEPDMA13_WIDTH 32
#define USB_DTXFSTS13 HW_REGISTER_RW( 0x7e980ab8 )
#define USB_DTXFSTS13_MASK 0xffffffff
#define USB_DTXFSTS13_WIDTH 32
#define USB_DIEPDMAB13 HW_REGISTER_RW( 0x7e980ab8 )
#define USB_DIEPDMAB13_MASK 0xffffffff
#define USB_DIEPDMAB13_WIDTH 32
#define USB_DIEPCTL14 HW_REGISTER_RW( 0x7e980ac0 )
#define USB_DIEPCTL14_MASK 0xffffffff
#define USB_DIEPCTL14_WIDTH 32
#define USB_DIEPINT14 HW_REGISTER_RW( 0x7e980ac8 )
#define USB_DIEPINT14_MASK 0xffffffff
#define USB_DIEPINT14_WIDTH 32
#define USB_DIEPTSIZ14 HW_REGISTER_RW( 0x7e980ad0 )
#define USB_DIEPTSIZ14_MASK 0xffffffff
#define USB_DIEPTSIZ14_WIDTH 32
#define USB_DIEPDMA14 HW_REGISTER_RW( 0x7e980ad4 )
#define USB_DIEPDMA14_MASK 0xffffffff
#define USB_DIEPDMA14_WIDTH 32
#define USB_DTXFSTS14 HW_REGISTER_RW( 0x7e980ad8 )
#define USB_DTXFSTS14_MASK 0xffffffff
#define USB_DTXFSTS14_WIDTH 32
#define USB_DIEPDMAB14 HW_REGISTER_RW( 0x7e980ad8 )
#define USB_DIEPDMAB14_MASK 0xffffffff
#define USB_DIEPDMAB14_WIDTH 32
#define USB_DIEPCTL15 HW_REGISTER_RW( 0x7e980ae0 )
#define USB_DIEPCTL15_MASK 0xffffffff
#define USB_DIEPCTL15_WIDTH 32
#define USB_DIEPINT15 HW_REGISTER_RW( 0x7e980ae8 )
#define USB_DIEPINT15_MASK 0xffffffff
#define USB_DIEPINT15_WIDTH 32
#define USB_DIEPTSIZ15 HW_REGISTER_RW( 0x7e980af0 )
#define USB_DIEPTSIZ15_MASK 0xffffffff
#define USB_DIEPTSIZ15_WIDTH 32
#define USB_DIEPDMA15 HW_REGISTER_RW( 0x7e980af4 )
#define USB_DIEPDMA15_MASK 0xffffffff
#define USB_DIEPDMA15_WIDTH 32
#define USB_DTXFSTS15 HW_REGISTER_RW( 0x7e980af8 )
#define USB_DTXFSTS15_MASK 0xffffffff
#define USB_DTXFSTS15_WIDTH 32
#define USB_DIEPDMAB15 HW_REGISTER_RW( 0x7e980af8 )
#define USB_DIEPDMAB15_MASK 0xffffffff
#define USB_DIEPDMAB15_WIDTH 32
#define USB_DOEPCTL0 HW_REGISTER_RW( 0x7e980b00 )
#define USB_DOEPCTL0_MASK 0xffffffff
#define USB_DOEPCTL0_WIDTH 32
#define USB_DOEPCTL0_ENA_BITS 31:31
#define USB_DOEPCTL0_ENA_SET 0x80000000
#define USB_DOEPCTL0_ENA_CLR 0x7fffffff
#define USB_DOEPCTL0_ENA_MSB 31
#define USB_DOEPCTL0_ENA_LSB 31
#define USB_DOEPCTL0_ENA_RESET 0x0
#define USB_DOEPCTL0_DIS_BITS 30:30
#define USB_DOEPCTL0_DIS_SET 0x40000000
#define USB_DOEPCTL0_DIS_CLR 0xbfffffff
#define USB_DOEPCTL0_DIS_MSB 30
#define USB_DOEPCTL0_DIS_LSB 30
#define USB_DOEPCTL0_DIS_RESET 0x0
#define USB_DOEPCTL0_SET_D1_PID_BITS 29:29
#define USB_DOEPCTL0_SET_D1_PID_SET 0x20000000
#define USB_DOEPCTL0_SET_D1_PID_CLR 0xdfffffff
#define USB_DOEPCTL0_SET_D1_PID_MSB 29
#define USB_DOEPCTL0_SET_D1_PID_LSB 29
#define USB_DOEPCTL0_SET_D1_PID_RESET 0x0
#define USB_DOEPCTL0_SET_ODD_FR_BITS 29:29
#define USB_DOEPCTL0_SET_ODD_FR_SET 0x20000000
#define USB_DOEPCTL0_SET_ODD_FR_CLR 0xdfffffff
#define USB_DOEPCTL0_SET_ODD_FR_MSB 29
#define USB_DOEPCTL0_SET_ODD_FR_LSB 29
#define USB_DOEPCTL0_SET_ODD_FR_RESET 0x0
#define USB_DOEPCTL0_SET_D0_PID_BITS 28:28
#define USB_DOEPCTL0_SET_D0_PID_SET 0x10000000
#define USB_DOEPCTL0_SET_D0_PID_CLR 0xefffffff
#define USB_DOEPCTL0_SET_D0_PID_MSB 28
#define USB_DOEPCTL0_SET_D0_PID_LSB 28
#define USB_DOEPCTL0_SET_D0_PID_RESET 0x0
#define USB_DOEPCTL0_SET_EVEN_FR_BITS 28:28
#define USB_DOEPCTL0_SET_EVEN_FR_SET 0x10000000
#define USB_DOEPCTL0_SET_EVEN_FR_CLR 0xefffffff
#define USB_DOEPCTL0_SET_EVEN_FR_MSB 28
#define USB_DOEPCTL0_SET_EVEN_FR_LSB 28
#define USB_DOEPCTL0_SET_EVEN_FR_RESET 0x0
#define USB_DOEPCTL0_SNAK_BITS 27:27
#define USB_DOEPCTL0_SNAK_SET 0x08000000
#define USB_DOEPCTL0_SNAK_CLR 0xf7ffffff
#define USB_DOEPCTL0_SNAK_MSB 27
#define USB_DOEPCTL0_SNAK_LSB 27
#define USB_DOEPCTL0_SNAK_RESET 0x0
#define USB_DOEPCTL0_CNAK_BITS 26:26
#define USB_DOEPCTL0_CNAK_SET 0x04000000
#define USB_DOEPCTL0_CNAK_CLR 0xfbffffff
#define USB_DOEPCTL0_CNAK_MSB 26
#define USB_DOEPCTL0_CNAK_LSB 26
#define USB_DOEPCTL0_CNAK_RESET 0x0
#define USB_DOEPCTL0_TXF_NUM_BITS 25:22
#define USB_DOEPCTL0_TXF_NUM_SET 0x03c00000
#define USB_DOEPCTL0_TXF_NUM_CLR 0xfc3fffff
#define USB_DOEPCTL0_TXF_NUM_MSB 25
#define USB_DOEPCTL0_TXF_NUM_LSB 22
#define USB_DOEPCTL0_TXF_NUM_RESET 0x0
#define USB_DOEPCTL0_STALL_BITS 21:21
#define USB_DOEPCTL0_STALL_SET 0x00200000
#define USB_DOEPCTL0_STALL_CLR 0xffdfffff
#define USB_DOEPCTL0_STALL_MSB 21
#define USB_DOEPCTL0_STALL_LSB 21
#define USB_DOEPCTL0_STALL_RESET 0x0
#define USB_DOEPCTL0_SNP_BITS 20:20
#define USB_DOEPCTL0_SNP_SET 0x00100000
#define USB_DOEPCTL0_SNP_CLR 0xffefffff
#define USB_DOEPCTL0_SNP_MSB 20
#define USB_DOEPCTL0_SNP_LSB 20
#define USB_DOEPCTL0_SNP_RESET 0x0
#define USB_DOEPCTL0_TYPE_BITS 19:18
#define USB_DOEPCTL0_TYPE_SET 0x000c0000
#define USB_DOEPCTL0_TYPE_CLR 0xfff3ffff
#define USB_DOEPCTL0_TYPE_MSB 19
#define USB_DOEPCTL0_TYPE_LSB 18
#define USB_DOEPCTL0_TYPE_RESET 0x0
#define USB_DOEPCTL0_NAK_STS_BITS 17:17
#define USB_DOEPCTL0_NAK_STS_SET 0x00020000
#define USB_DOEPCTL0_NAK_STS_CLR 0xfffdffff
#define USB_DOEPCTL0_NAK_STS_MSB 17
#define USB_DOEPCTL0_NAK_STS_LSB 17
#define USB_DOEPCTL0_NAK_STS_RESET 0x0
#define USB_DOEPCTL0_DPID_BITS 16:16
#define USB_DOEPCTL0_DPID_SET 0x00010000
#define USB_DOEPCTL0_DPID_CLR 0xfffeffff
#define USB_DOEPCTL0_DPID_MSB 16
#define USB_DOEPCTL0_DPID_LSB 16
#define USB_DOEPCTL0_DPID_RESET 0x0
#define USB_DOEPCTL0_EO_FR_NUM_BITS 16:16
#define USB_DOEPCTL0_EO_FR_NUM_SET 0x00010000
#define USB_DOEPCTL0_EO_FR_NUM_CLR 0xfffeffff
#define USB_DOEPCTL0_EO_FR_NUM_MSB 16
#define USB_DOEPCTL0_EO_FR_NUM_LSB 16
#define USB_DOEPCTL0_EO_FR_NUM_RESET 0x0
#define USB_DOEPCTL0_USB_ACT_EP_BITS 15:15
#define USB_DOEPCTL0_USB_ACT_EP_SET 0x00008000
#define USB_DOEPCTL0_USB_ACT_EP_CLR 0xffff7fff
#define USB_DOEPCTL0_USB_ACT_EP_MSB 15
#define USB_DOEPCTL0_USB_ACT_EP_LSB 15
#define USB_DOEPCTL0_USB_ACT_EP_RESET 0x0
#define USB_DOEPCTL0_NEXT_EP_BITS 14:11
#define USB_DOEPCTL0_NEXT_EP_SET 0x00007800
#define USB_DOEPCTL0_NEXT_EP_CLR 0xffff87ff
#define USB_DOEPCTL0_NEXT_EP_MSB 14
#define USB_DOEPCTL0_NEXT_EP_LSB 11
#define USB_DOEPCTL0_NEXT_EP_RESET 0x0
#define USB_DOEPCTL0_MPS_BITS 10:0
#define USB_DOEPCTL0_MPS_SET 0x000007ff
#define USB_DOEPCTL0_MPS_CLR 0xfffff800
#define USB_DOEPCTL0_MPS_MSB 10
#define USB_DOEPCTL0_MPS_LSB 0
#define USB_DOEPCTL0_MPS_RESET 0x0
#define USB_DOEPINT0 HW_REGISTER_RW( 0x7e980b08 )
#define USB_DOEPINT0_MASK 0xffffffff
#define USB_DOEPINT0_WIDTH 32
#define USB_DOEPINT0_BNA_BITS 9:9
#define USB_DOEPINT0_BNA_SET 0x00000200
#define USB_DOEPINT0_BNA_CLR 0xfffffdff
#define USB_DOEPINT0_BNA_MSB 9
#define USB_DOEPINT0_BNA_LSB 9
#define USB_DOEPINT0_BNA_RESET 0x0
#define USB_DOEPINT0_TX_FIFO_UNDRN_BITS 8:8
#define USB_DOEPINT0_TX_FIFO_UNDRN_SET 0x00000100
#define USB_DOEPINT0_TX_FIFO_UNDRN_CLR 0xfffffeff
#define USB_DOEPINT0_TX_FIFO_UNDRN_MSB 8
#define USB_DOEPINT0_TX_FIFO_UNDRN_LSB 8
#define USB_DOEPINT0_TX_FIFO_UNDRN_RESET 0x0
#define USB_DOEPINT0_OUT_PKT_ERR_BITS 8:8
#define USB_DOEPINT0_OUT_PKT_ERR_SET 0x00000100
#define USB_DOEPINT0_OUT_PKT_ERR_CLR 0xfffffeff
#define USB_DOEPINT0_OUT_PKT_ERR_MSB 8
#define USB_DOEPINT0_OUT_PKT_ERR_LSB 8
#define USB_DOEPINT0_OUT_PKT_ERR_RESET 0x0
#define USB_DOEPINT0_TXF_EMPTY_BITS 7:7
#define USB_DOEPINT0_TXF_EMPTY_SET 0x00000080
#define USB_DOEPINT0_TXF_EMPTY_CLR 0xffffff7f
#define USB_DOEPINT0_TXF_EMPTY_MSB 7
#define USB_DOEPINT0_TXF_EMPTY_LSB 7
#define USB_DOEPINT0_TXF_EMPTY_RESET 0x0
#define USB_DOEPINT0_IN_EP_NAK_EFF_BITS 6:6
#define USB_DOEPINT0_IN_EP_NAK_EFF_SET 0x00000040
#define USB_DOEPINT0_IN_EP_NAK_EFF_CLR 0xffffffbf
#define USB_DOEPINT0_IN_EP_NAK_EFF_MSB 6
#define USB_DOEPINT0_IN_EP_NAK_EFF_LSB 6
#define USB_DOEPINT0_IN_EP_NAK_EFF_RESET 0x0
#define USB_DOEPINT0_BACK2BACK_SETUP_BITS 6:6
#define USB_DOEPINT0_BACK2BACK_SETUP_SET 0x00000040
#define USB_DOEPINT0_BACK2BACK_SETUP_CLR 0xffffffbf
#define USB_DOEPINT0_BACK2BACK_SETUP_MSB 6
#define USB_DOEPINT0_BACK2BACK_SETUP_LSB 6
#define USB_DOEPINT0_BACK2BACK_SETUP_RESET 0x0
#define USB_DOEPINT0_IN_TKN_EP_MIS_BITS 5:5
#define USB_DOEPINT0_IN_TKN_EP_MIS_SET 0x00000020
#define USB_DOEPINT0_IN_TKN_EP_MIS_CLR 0xffffffdf
#define USB_DOEPINT0_IN_TKN_EP_MIS_MSB 5
#define USB_DOEPINT0_IN_TKN_EP_MIS_LSB 5
#define USB_DOEPINT0_IN_TKN_EP_MIS_RESET 0x0
#define USB_DOEPINT0_STS_PHSE_RCVD_BITS 5:5
#define USB_DOEPINT0_STS_PHSE_RCVD_SET 0x00000020
#define USB_DOEPINT0_STS_PHSE_RCVD_CLR 0xffffffdf
#define USB_DOEPINT0_STS_PHSE_RCVD_MSB 5
#define USB_DOEPINT0_STS_PHSE_RCVD_LSB 5
#define USB_DOEPINT0_STS_PHSE_RCVD_RESET 0x0
#define USB_DOEPINT0_IN_TKN_TXFEMP_BITS 4:4
#define USB_DOEPINT0_IN_TKN_TXFEMP_SET 0x00000010
#define USB_DOEPINT0_IN_TKN_TXFEMP_CLR 0xffffffef
#define USB_DOEPINT0_IN_TKN_TXFEMP_MSB 4
#define USB_DOEPINT0_IN_TKN_TXFEMP_LSB 4
#define USB_DOEPINT0_IN_TKN_TXFEMP_RESET 0x0
#define USB_DOEPINT0_OUT_TKN_EP_DIS_BITS 4:4
#define USB_DOEPINT0_OUT_TKN_EP_DIS_SET 0x00000010
#define USB_DOEPINT0_OUT_TKN_EP_DIS_CLR 0xffffffef
#define USB_DOEPINT0_OUT_TKN_EP_DIS_MSB 4
#define USB_DOEPINT0_OUT_TKN_EP_DIS_LSB 4
#define USB_DOEPINT0_OUT_TKN_EP_DIS_RESET 0x0
#define USB_DOEPINT0_TIMEOUT_BITS 3:3
#define USB_DOEPINT0_TIMEOUT_SET 0x00000008
#define USB_DOEPINT0_TIMEOUT_CLR 0xfffffff7
#define USB_DOEPINT0_TIMEOUT_MSB 3
#define USB_DOEPINT0_TIMEOUT_LSB 3
#define USB_DOEPINT0_TIMEOUT_RESET 0x0
#define USB_DOEPINT0_SETUP_BITS 3:3
#define USB_DOEPINT0_SETUP_SET 0x00000008
#define USB_DOEPINT0_SETUP_CLR 0xfffffff7
#define USB_DOEPINT0_SETUP_MSB 3
#define USB_DOEPINT0_SETUP_LSB 3
#define USB_DOEPINT0_SETUP_RESET 0x0
#define USB_DOEPINT0_AHB_ERR_BITS 2:2
#define USB_DOEPINT0_AHB_ERR_SET 0x00000004
#define USB_DOEPINT0_AHB_ERR_CLR 0xfffffffb
#define USB_DOEPINT0_AHB_ERR_MSB 2
#define USB_DOEPINT0_AHB_ERR_LSB 2
#define USB_DOEPINT0_AHB_ERR_RESET 0x0
#define USB_DOEPINT0_EP_DISBLD_BITS 1:1
#define USB_DOEPINT0_EP_DISBLD_SET 0x00000002
#define USB_DOEPINT0_EP_DISBLD_CLR 0xfffffffd
#define USB_DOEPINT0_EP_DISBLD_MSB 1
#define USB_DOEPINT0_EP_DISBLD_LSB 1
#define USB_DOEPINT0_EP_DISBLD_RESET 0x0
#define USB_DOEPINT0_XFER_COMPL_BITS 0:0
#define USB_DOEPINT0_XFER_COMPL_SET 0x00000001
#define USB_DOEPINT0_XFER_COMPL_CLR 0xfffffffe
#define USB_DOEPINT0_XFER_COMPL_MSB 0
#define USB_DOEPINT0_XFER_COMPL_LSB 0
#define USB_DOEPINT0_XFER_COMPL_RESET 0x0
#define USB_DOEPTSIZ0 HW_REGISTER_RW( 0x7e980b10 )
#define USB_DOEPTSIZ0_MASK 0xffffffff
#define USB_DOEPTSIZ0_WIDTH 32
#define USB_DOEPTSIZ0_SUP_CNT_BITS 30:29
#define USB_DOEPTSIZ0_SUP_CNT_SET 0x60000000
#define USB_DOEPTSIZ0_SUP_CNT_CLR 0x9fffffff
#define USB_DOEPTSIZ0_SUP_CNT_MSB 30
#define USB_DOEPTSIZ0_SUP_CNT_LSB 29
#define USB_DOEPTSIZ0_SUP_CNT_RESET 0x0
#define USB_DOEPTSIZ0_RX_DPID_BITS 30:29
#define USB_DOEPTSIZ0_RX_DPID_SET 0x60000000
#define USB_DOEPTSIZ0_RX_DPID_CLR 0x9fffffff
#define USB_DOEPTSIZ0_RX_DPID_MSB 30
#define USB_DOEPTSIZ0_RX_DPID_LSB 29
#define USB_DOEPTSIZ0_RX_DPID_RESET 0x0
#define USB_DOEPTSIZ0_MC_BITS 30:29
#define USB_DOEPTSIZ0_MC_SET 0x60000000
#define USB_DOEPTSIZ0_MC_CLR 0x9fffffff
#define USB_DOEPTSIZ0_MC_MSB 30
#define USB_DOEPTSIZ0_MC_LSB 29
#define USB_DOEPTSIZ0_MC_RESET 0x0
#define USB_DOEPTSIZ0_PKT_CNT_BITS 28:19
#define USB_DOEPTSIZ0_PKT_CNT_SET 0x1ff80000
#define USB_DOEPTSIZ0_PKT_CNT_CLR 0xe007ffff
#define USB_DOEPTSIZ0_PKT_CNT_MSB 28
#define USB_DOEPTSIZ0_PKT_CNT_LSB 19
#define USB_DOEPTSIZ0_PKT_CNT_RESET 0x0
#define USB_DOEPTSIZ0_XFERSIZE_BITS 18:0
#define USB_DOEPTSIZ0_XFERSIZE_SET 0x0007ffff
#define USB_DOEPTSIZ0_XFERSIZE_CLR 0xfff80000
#define USB_DOEPTSIZ0_XFERSIZE_MSB 18
#define USB_DOEPTSIZ0_XFERSIZE_LSB 0
#define USB_DOEPTSIZ0_XFERSIZE_RESET 0x0
#define USB_DOEPDMA0 HW_REGISTER_RW( 0x7e980b14 )
#define USB_DOEPDMA0_MASK 0xffffffff
#define USB_DOEPDMA0_WIDTH 32
#define USB_DOEPDMAB0 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB0_MASK 0xffffffff
#define USB_DOEPDMAB0_WIDTH 32
#define USB_DOEPCTL1 HW_REGISTER_RW( 0x7e980b20 )
#define USB_DOEPCTL1_MASK 0xffffffff
#define USB_DOEPCTL1_WIDTH 32
#define USB_DOEPINT1 HW_REGISTER_RW( 0x7e980b28 )
#define USB_DOEPINT1_MASK 0xffffffff
#define USB_DOEPINT1_WIDTH 32
#define USB_DOEPTSIZ1 HW_REGISTER_RW( 0x7e980b30 )
#define USB_DOEPTSIZ1_MASK 0xffffffff
#define USB_DOEPTSIZ1_WIDTH 32
#define USB_DOEPDMA1 HW_REGISTER_RW( 0x7e980b34 )
#define USB_DOEPDMA1_MASK 0xffffffff
#define USB_DOEPDMA1_WIDTH 32
#define USB_DOEPDMAB1 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB1_MASK 0xffffffff
#define USB_DOEPDMAB1_WIDTH 32
#define USB_DOEPCTL2 HW_REGISTER_RW( 0x7e980b40 )
#define USB_DOEPCTL2_MASK 0xffffffff
#define USB_DOEPCTL2_WIDTH 32
#define USB_DOEPINT2 HW_REGISTER_RW( 0x7e980b48 )
#define USB_DOEPINT2_MASK 0xffffffff
#define USB_DOEPINT2_WIDTH 32
#define USB_DOEPTSIZ2 HW_REGISTER_RW( 0x7e980b50 )
#define USB_DOEPTSIZ2_MASK 0xffffffff
#define USB_DOEPTSIZ2_WIDTH 32
#define USB_DOEPDMA2 HW_REGISTER_RW( 0x7e980b54 )
#define USB_DOEPDMA2_MASK 0xffffffff
#define USB_DOEPDMA2_WIDTH 32
#define USB_DOEPDMAB2 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB2_MASK 0xffffffff
#define USB_DOEPDMAB2_WIDTH 32
#define USB_DOEPCTL3 HW_REGISTER_RW( 0x7e980b60 )
#define USB_DOEPCTL3_MASK 0xffffffff
#define USB_DOEPCTL3_WIDTH 32
#define USB_DOEPINT3 HW_REGISTER_RW( 0x7e980b68 )
#define USB_DOEPINT3_MASK 0xffffffff
#define USB_DOEPINT3_WIDTH 32
#define USB_DOEPTSIZ3 HW_REGISTER_RW( 0x7e980b70 )
#define USB_DOEPTSIZ3_MASK 0xffffffff
#define USB_DOEPTSIZ3_WIDTH 32
#define USB_DOEPDMA3 HW_REGISTER_RW( 0x7e980b74 )
#define USB_DOEPDMA3_MASK 0xffffffff
#define USB_DOEPDMA3_WIDTH 32
#define USB_DOEPDMAB3 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB3_MASK 0xffffffff
#define USB_DOEPDMAB3_WIDTH 32
#define USB_DOEPCTL4 HW_REGISTER_RW( 0x7e980b80 )
#define USB_DOEPCTL4_MASK 0xffffffff
#define USB_DOEPCTL4_WIDTH 32
#define USB_DOEPINT4 HW_REGISTER_RW( 0x7e980b88 )
#define USB_DOEPINT4_MASK 0xffffffff
#define USB_DOEPINT4_WIDTH 32
#define USB_DOEPTSIZ4 HW_REGISTER_RW( 0x7e980b90 )
#define USB_DOEPTSIZ4_MASK 0xffffffff
#define USB_DOEPTSIZ4_WIDTH 32
#define USB_DOEPDMA4 HW_REGISTER_RW( 0x7e980b94 )
#define USB_DOEPDMA4_MASK 0xffffffff
#define USB_DOEPDMA4_WIDTH 32
#define USB_DOEPDMAB4 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB4_MASK 0xffffffff
#define USB_DOEPDMAB4_WIDTH 32
#define USB_DOEPCTL5 HW_REGISTER_RW( 0x7e980ba0 )
#define USB_DOEPCTL5_MASK 0xffffffff
#define USB_DOEPCTL5_WIDTH 32
#define USB_DOEPINT5 HW_REGISTER_RW( 0x7e980ba8 )
#define USB_DOEPINT5_MASK 0xffffffff
#define USB_DOEPINT5_WIDTH 32
#define USB_DOEPTSIZ5 HW_REGISTER_RW( 0x7e980bb0 )
#define USB_DOEPTSIZ5_MASK 0xffffffff
#define USB_DOEPTSIZ5_WIDTH 32
#define USB_DOEPDMA5 HW_REGISTER_RW( 0x7e980bb4 )
#define USB_DOEPDMA5_MASK 0xffffffff
#define USB_DOEPDMA5_WIDTH 32
#define USB_DOEPDMAB5 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB5_MASK 0xffffffff
#define USB_DOEPDMAB5_WIDTH 32
#define USB_DOEPCTL6 HW_REGISTER_RW( 0x7e980bc0 )
#define USB_DOEPCTL6_MASK 0xffffffff
#define USB_DOEPCTL6_WIDTH 32
#define USB_DOEPINT6 HW_REGISTER_RW( 0x7e980bc8 )
#define USB_DOEPINT6_MASK 0xffffffff
#define USB_DOEPINT6_WIDTH 32
#define USB_DOEPTSIZ6 HW_REGISTER_RW( 0x7e980bd0 )
#define USB_DOEPTSIZ6_MASK 0xffffffff
#define USB_DOEPTSIZ6_WIDTH 32
#define USB_DOEPDMA6 HW_REGISTER_RW( 0x7e980bd4 )
#define USB_DOEPDMA6_MASK 0xffffffff
#define USB_DOEPDMA6_WIDTH 32
#define USB_DOEPDMAB6 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB6_MASK 0xffffffff
#define USB_DOEPDMAB6_WIDTH 32
#define USB_DOEPCTL7 HW_REGISTER_RW( 0x7e980be0 )
#define USB_DOEPCTL7_MASK 0xffffffff
#define USB_DOEPCTL7_WIDTH 32
#define USB_DOEPINT7 HW_REGISTER_RW( 0x7e980be8 )
#define USB_DOEPINT7_MASK 0xffffffff
#define USB_DOEPINT7_WIDTH 32
#define USB_DOEPTSIZ7 HW_REGISTER_RW( 0x7e980bf0 )
#define USB_DOEPTSIZ7_MASK 0xffffffff
#define USB_DOEPTSIZ7_WIDTH 32
#define USB_DOEPDMA7 HW_REGISTER_RW( 0x7e980bf4 )
#define USB_DOEPDMA7_MASK 0xffffffff
#define USB_DOEPDMA7_WIDTH 32
#define USB_DOEPDMAB7 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB7_MASK 0xffffffff
#define USB_DOEPDMAB7_WIDTH 32
#define USB_DOEPCTL8 HW_REGISTER_RW( 0x7e980c00 )
#define USB_DOEPCTL8_MASK 0xffffffff
#define USB_DOEPCTL8_WIDTH 32
#define USB_DOEPINT8 HW_REGISTER_RW( 0x7e980c08 )
#define USB_DOEPINT8_MASK 0xffffffff
#define USB_DOEPINT8_WIDTH 32
#define USB_DOEPTSIZ8 HW_REGISTER_RW( 0x7e980c10 )
#define USB_DOEPTSIZ8_MASK 0xffffffff
#define USB_DOEPTSIZ8_WIDTH 32
#define USB_DOEPDMA8 HW_REGISTER_RW( 0x7e980c14 )
#define USB_DOEPDMA8_MASK 0xffffffff
#define USB_DOEPDMA8_WIDTH 32
#define USB_DOEPDMAB8 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB8_MASK 0xffffffff
#define USB_DOEPDMAB8_WIDTH 32
#define USB_DOEPCTL9 HW_REGISTER_RW( 0x7e980c20 )
#define USB_DOEPCTL9_MASK 0xffffffff
#define USB_DOEPCTL9_WIDTH 32
#define USB_DOEPINT9 HW_REGISTER_RW( 0x7e980c28 )
#define USB_DOEPINT9_MASK 0xffffffff
#define USB_DOEPINT9_WIDTH 32
#define USB_DOEPTSIZ9 HW_REGISTER_RW( 0x7e980c30 )
#define USB_DOEPTSIZ9_MASK 0xffffffff
#define USB_DOEPTSIZ9_WIDTH 32
#define USB_DOEPDMA9 HW_REGISTER_RW( 0x7e980c34 )
#define USB_DOEPDMA9_MASK 0xffffffff
#define USB_DOEPDMA9_WIDTH 32
#define USB_DOEPDMAB9 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB9_MASK 0xffffffff
#define USB_DOEPDMAB9_WIDTH 32
#define USB_DOEPCTL10 HW_REGISTER_RW( 0x7e980c40 )
#define USB_DOEPCTL10_MASK 0xffffffff
#define USB_DOEPCTL10_WIDTH 32
#define USB_DOEPINT10 HW_REGISTER_RW( 0x7e980c48 )
#define USB_DOEPINT10_MASK 0xffffffff
#define USB_DOEPINT10_WIDTH 32
#define USB_DOEPTSIZ10 HW_REGISTER_RW( 0x7e980c50 )
#define USB_DOEPTSIZ10_MASK 0xffffffff
#define USB_DOEPTSIZ10_WIDTH 32
#define USB_DOEPDMA10 HW_REGISTER_RW( 0x7e980c54 )
#define USB_DOEPDMA10_MASK 0xffffffff
#define USB_DOEPDMA10_WIDTH 32
#define USB_DOEPDMAB10 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB10_MASK 0xffffffff
#define USB_DOEPDMAB10_WIDTH 32
#define USB_DOEPCTL11 HW_REGISTER_RW( 0x7e980c60 )
#define USB_DOEPCTL11_MASK 0xffffffff
#define USB_DOEPCTL11_WIDTH 32
#define USB_DOEPINT11 HW_REGISTER_RW( 0x7e980c68 )
#define USB_DOEPINT11_MASK 0xffffffff
#define USB_DOEPINT11_WIDTH 32
#define USB_DOEPTSIZ11 HW_REGISTER_RW( 0x7e980c70 )
#define USB_DOEPTSIZ11_MASK 0xffffffff
#define USB_DOEPTSIZ11_WIDTH 32
#define USB_DOEPDMA11 HW_REGISTER_RW( 0x7e980c74 )
#define USB_DOEPDMA11_MASK 0xffffffff
#define USB_DOEPDMA11_WIDTH 32
#define USB_DOEPDMAB11 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB11_MASK 0xffffffff
#define USB_DOEPDMAB11_WIDTH 32
#define USB_DOEPCTL12 HW_REGISTER_RW( 0x7e980c80 )
#define USB_DOEPCTL12_MASK 0xffffffff
#define USB_DOEPCTL12_WIDTH 32
#define USB_DOEPINT12 HW_REGISTER_RW( 0x7e980c88 )
#define USB_DOEPINT12_MASK 0xffffffff
#define USB_DOEPINT12_WIDTH 32
#define USB_DOEPTSIZ12 HW_REGISTER_RW( 0x7e980c90 )
#define USB_DOEPTSIZ12_MASK 0xffffffff
#define USB_DOEPTSIZ12_WIDTH 32
#define USB_DOEPDMA12 HW_REGISTER_RW( 0x7e980c94 )
#define USB_DOEPDMA12_MASK 0xffffffff
#define USB_DOEPDMA12_WIDTH 32
#define USB_DOEPDMAB12 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB12_MASK 0xffffffff
#define USB_DOEPDMAB12_WIDTH 32
#define USB_DOEPCTL13 HW_REGISTER_RW( 0x7e980ca0 )
#define USB_DOEPCTL13_MASK 0xffffffff
#define USB_DOEPCTL13_WIDTH 32
#define USB_DOEPINT13 HW_REGISTER_RW( 0x7e980ca8 )
#define USB_DOEPINT13_MASK 0xffffffff
#define USB_DOEPINT13_WIDTH 32
#define USB_DOEPTSIZ13 HW_REGISTER_RW( 0x7e980cb0 )
#define USB_DOEPTSIZ13_MASK 0xffffffff
#define USB_DOEPTSIZ13_WIDTH 32
#define USB_DOEPDMA13 HW_REGISTER_RW( 0x7e980cb4 )
#define USB_DOEPDMA13_MASK 0xffffffff
#define USB_DOEPDMA13_WIDTH 32
#define USB_DOEPDMAB13 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB13_MASK 0xffffffff
#define USB_DOEPDMAB13_WIDTH 32
#define USB_DOEPCTL14 HW_REGISTER_RW( 0x7e980cc0 )
#define USB_DOEPCTL14_MASK 0xffffffff
#define USB_DOEPCTL14_WIDTH 32
#define USB_DOEPINT14 HW_REGISTER_RW( 0x7e980cc8 )
#define USB_DOEPINT14_MASK 0xffffffff
#define USB_DOEPINT14_WIDTH 32
#define USB_DOEPTSIZ14 HW_REGISTER_RW( 0x7e980cd0 )
#define USB_DOEPTSIZ14_MASK 0xffffffff
#define USB_DOEPTSIZ14_WIDTH 32
#define USB_DOEPDMA14 HW_REGISTER_RW( 0x7e980cd4 )
#define USB_DOEPDMA14_MASK 0xffffffff
#define USB_DOEPDMA14_WIDTH 32
#define USB_DOEPDMAB14 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB14_MASK 0xffffffff
#define USB_DOEPDMAB14_WIDTH 32
#define USB_DOEPCTL15 HW_REGISTER_RW( 0x7e980ce0 )
#define USB_DOEPCTL15_MASK 0xffffffff
#define USB_DOEPCTL15_WIDTH 32
#define USB_DOEPINT15 HW_REGISTER_RW( 0x7e980ce8 )
#define USB_DOEPINT15_MASK 0xffffffff
#define USB_DOEPINT15_WIDTH 32
#define USB_DOEPTSIZ15 HW_REGISTER_RW( 0x7e980cf0 )
#define USB_DOEPTSIZ15_MASK 0xffffffff
#define USB_DOEPTSIZ15_WIDTH 32
#define USB_DOEPDMA15 HW_REGISTER_RW( 0x7e980cf4 )
#define USB_DOEPDMA15_MASK 0xffffffff
#define USB_DOEPDMA15_WIDTH 32
#define USB_DOEPDMAB15 HW_REGISTER_RW( 0x7e980b1c )
#define USB_DOEPDMAB15_MASK 0xffffffff
#define USB_DOEPDMAB15_WIDTH 32
#define USB_PCGCR HW_REGISTER_RW( 0x7e980e00 )
#define USB_PCGCR_MASK 0x0000000f
#define USB_PCGCR_WIDTH 4
#define USB_PCGCR_RST_PDWN_MODULE_BITS 3:3
#define USB_PCGCR_RST_PDWN_MODULE_SET 0x00000008
#define USB_PCGCR_RST_PDWN_MODULE_CLR 0xfffffff7
#define USB_PCGCR_RST_PDWN_MODULE_MSB 3
#define USB_PCGCR_RST_PDWN_MODULE_LSB 3
#define USB_PCGCR_RST_PDWN_MODULE_RESET 0x0
#define USB_PCGCR_PWR_CLMP_BITS 2:2
#define USB_PCGCR_PWR_CLMP_SET 0x00000004
#define USB_PCGCR_PWR_CLMP_CLR 0xfffffffb
#define USB_PCGCR_PWR_CLMP_MSB 2
#define USB_PCGCR_PWR_CLMP_LSB 2
#define USB_PCGCR_PWR_CLMP_RESET 0x0
#define USB_PCGCR_GATE_HCLK_BITS 1:1
#define USB_PCGCR_GATE_HCLK_SET 0x00000002
#define USB_PCGCR_GATE_HCLK_CLR 0xfffffffd
#define USB_PCGCR_GATE_HCLK_MSB 1
#define USB_PCGCR_GATE_HCLK_LSB 1
#define USB_PCGCR_GATE_HCLK_RESET 0x0
#define USB_PCGCR_STOP_PCLK_BITS 0:0
#define USB_PCGCR_STOP_PCLK_SET 0x00000001
#define USB_PCGCR_STOP_PCLK_CLR 0xfffffffe
#define USB_PCGCR_STOP_PCLK_MSB 0
#define USB_PCGCR_STOP_PCLK_LSB 0
#define USB_PCGCR_STOP_PCLK_RESET 0x0
#define USB_DFIFO0 HW_REGISTER_RW( 0x7e981000 )
#define USB_DFIFO0_MASK 0xffffffff
#define USB_DFIFO0_WIDTH 32
#define USB_DFIFO1 HW_REGISTER_RW( 0x7e982000 )
#define USB_DFIFO1_MASK 0xffffffff
#define USB_DFIFO1_WIDTH 32
#define USB_DFIFO2 HW_REGISTER_RW( 0x7e983000 )
#define USB_DFIFO2_MASK 0xffffffff
#define USB_DFIFO2_WIDTH 32
#define USB_DFIFO3 HW_REGISTER_RW( 0x7e984000 )
#define USB_DFIFO3_MASK 0xffffffff
#define USB_DFIFO3_WIDTH 32
#define USB_DFIFO4 HW_REGISTER_RW( 0x7e985000 )
#define USB_DFIFO4_MASK 0xffffffff
#define USB_DFIFO4_WIDTH 32
#define USB_DFIFO5 HW_REGISTER_RW( 0x7e986000 )
#define USB_DFIFO5_MASK 0xffffffff
#define USB_DFIFO5_WIDTH 32
#define USB_DFIFO6 HW_REGISTER_RW( 0x7e987000 )
#define USB_DFIFO6_MASK 0xffffffff
#define USB_DFIFO6_WIDTH 32
#define USB_DFIFO7 HW_REGISTER_RW( 0x7e988000 )
#define USB_DFIFO7_MASK 0xffffffff
#define USB_DFIFO7_WIDTH 32
#define USB_DFIFO8 HW_REGISTER_RW( 0x7e989000 )
#define USB_DFIFO8_MASK 0xffffffff
#define USB_DFIFO8_WIDTH 32
#define USB_DFIFO9 HW_REGISTER_RW( 0x7e98a000 )
#define USB_DFIFO9_MASK 0xffffffff
#define USB_DFIFO9_WIDTH 32
#define USB_DFIFO10 HW_REGISTER_RW( 0x7e98b000 )
#define USB_DFIFO10_MASK 0xffffffff
#define USB_DFIFO10_WIDTH 32
#define USB_DFIFO11 HW_REGISTER_RW( 0x7e98c000 )
#define USB_DFIFO11_MASK 0xffffffff
#define USB_DFIFO11_WIDTH 32
#define USB_DFIFO12 HW_REGISTER_RW( 0x7e98d000 )
#define USB_DFIFO12_MASK 0xffffffff
#define USB_DFIFO12_WIDTH 32
#define USB_DFIFO13 HW_REGISTER_RW( 0x7e98e000 )
#define USB_DFIFO13_MASK 0xffffffff
#define USB_DFIFO13_WIDTH 32
#define USB_DFIFO14 HW_REGISTER_RW( 0x7e98f000 )
#define USB_DFIFO14_MASK 0xffffffff
#define USB_DFIFO14_WIDTH 32
#define USB_DFIFO15 HW_REGISTER_RW( 0x7e990000 )
#define USB_DFIFO15_MASK 0xffffffff
#define USB_DFIFO15_WIDTH 32
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