1830 lines
88 KiB
C
Executable File
1830 lines
88 KiB
C
Executable File
/*=============================================================================
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Copyright (c) 2006 Broadcom Europe Limited.
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All rights reserved.
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Project : VideoCore
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Module : VideoCore hardware headers
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File : $Id$
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FILE DESCRIPTION
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Public interface definition file for hardware specified registers.
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=============================================================================*/
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#ifndef _HARDWARE_VC4_H
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#define _HARDWARE_VC4_H
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/********************************************************
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* VideoCore IV support
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********************************************************/
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/*
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VC4 Processor Control Register usage
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p0 PRFPXCS - See "Scalar Floating Point Exception Control" in the VCIV Architecture Specification.
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p1 PRCANARY - If stack protection is enabled, this register holds the canary.
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p2-p9 Unassigned
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p10 [B0] PRPOWCTL - Closely Coupled Power Control (VPU clock gating)
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p11 [B0] PRTIMCTL - Closely Coupled Timer Control (core and sleep timers)
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p12 [B0] PRCORTIM - Core Timer Result
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p13 [B0] PRSLPTIM - Sleep Timer Result
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p14 PROWCNT - Count of outstanding writes. See "Scalar Memory Engine" in the VC4AS.
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p15 PRORCNT - Count of outstanding reads. See "Scalar Memory Engine" in the VC4AS.
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p16-p31 are single-bit mutexes, shared between the two VPUs. See "P-Reg Semaphore" in the VC4AS.
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p16 PRSPINL - Used by spinlock, a lightweight mutex.
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p17 - Used by vcos_quickslow_mutex on ThreadX. (TODO: could we just use p16 instead?)
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p18 Unassigned
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p19 Unassigned
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p20 Unassigned
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p21 Unassigned
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p22 Unassigned
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p23 Unassigned
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p24 Unassigned
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p25 Unassigned
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p26 Unassigned
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p27 Unassigned
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p28 Unassigned
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p29 Unassigned
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p30 Unassigned
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p31 Unassigned
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*/
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//#define FORCE_SECOND_CORE
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#include "bcm2708_chip/arm_control.h"
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#include "bcm2708_chip/apb_async_bridge_ctrl.h"
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#include "bcm2708_chip/axi_dma0.h"
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#ifdef __BCM2708A0__
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#include "bcm2708_chip/axi_dma8.h"
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#else
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#include "bcm2708_chip/axi_dma15.h"
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#endif
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#ifdef __BCM2708A0__
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#include "bcm2708_chip/cam0_a0.h"
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#include "bcm2708_chip/cam1_a0.h"
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#include "bcm2708_chip/ccp2tx_a0.h"
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#else
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#include "bcm2708_chip/cam0.h"
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#include "bcm2708_chip/cam1.h"
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#include "bcm2708_chip/ccp2tx.h"
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#endif
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#include "bcm2708_chip/clkman_image.h"
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// #include "bcm2708_chip/clkman_audio.h"
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// #include "bcm2708_chip/clkman_run.h"
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#include "bcm2708_chip/cpg.h"
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#ifdef __BCM2708A0__
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#include "bcm2708_chip/cpr_clkman_a0.h"
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#include "bcm2708_chip/cpr_powman_a0.h"
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#include "bcm2708_chip/cpr_apb2wtap_a0.h"
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#else
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#include "bcm2708_chip/cpr_clkman.h"
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#include "bcm2708_chip/cpr_powman.h"
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#include "bcm2708_chip/cpr_apb2wtap.h"
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#endif
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#include "bcm2708_chip/dpi.h"
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#include "bcm2708_chip/dsi.h"
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#include "bcm2708_chip/dsi4.h"
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#include "bcm2708_chip/gpio.h"
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#include "bcm2708_chip/hdcp.h"
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#include "bcm2708_chip/hdmi.h"
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#include "bcm2708_chip/hdmicore.h"
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#include "bcm2708_chip/hvs.h"
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#include "bcm2708_chip/i2c0.h"
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#include "bcm2708_chip/i2c1.h"
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#include "bcm2708_chip/i2c2.h"
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#include "bcm2708_chip/intctrl0.h"
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#include "bcm2708_chip/intctrl1.h"
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#include "bcm2708_chip/isp.h"
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#include "bcm2708_chip/l2_cache_ctrl.h"
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#include "bcm2708_chip/jpeg_top.h"
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#include "bcm2708_chip/mphi.h"
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#include "bcm2708_chip/multicore_sync.h"
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#include "bcm2708_chip/nexus_uba.h"
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#include "bcm2708_chip/otp.h"
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#include "bcm2708_chip/pcm.h"
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#include "bcm2708_chip/perfmon.h"
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#include "bcm2708_chip/pixel_valve0.h"
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#include "bcm2708_chip/pixel_valve1.h"
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#include "bcm2708_chip/pixel_valve2.h"
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#include "bcm2708_chip/pwm.h"
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// #include "bcm2708_chip/reset_ctrl.h"
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#include "bcm2708_chip/sdc_ctrl.h"
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#include "bcm2708_chip/sdc_addr_front.h"
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#include "bcm2708_chip/sdc_dq_front.h"
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#include "bcm2708_chip/sdhost.h"
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#if defined(__BCM2708A0__)
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#include "bcm2708_chip/slimbus_a0.h"
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#else
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#include "bcm2708_chip/slimbus.h"
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#endif
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#include "bcm2708_chip/spi_master.h"
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#include "bcm2708_chip/system_arbiter_ctrl.h"
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#include "bcm2708_chip/vpu_arb_ctrl.h"
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#include "bcm2708_chip/peri_image_arb_ctrl.h"
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#ifdef __BCM2708A0__
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#include "bcm2708_chip/tectl_a0.h"
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#else
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#include "bcm2708_chip/tectl.h"
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#endif
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#include "bcm2708_chip/timer.h"
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#include "bcm2708_chip/tempsens.h"
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#include "bcm2708_chip/txp.h"
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#include "bcm2708_chip/uart.h"
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#include "bcm2708_chip/v3d.h"
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#include "bcm2708_chip/vec.h"
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#include "bcm2708_chip/vpu_l1_cache_ctrl.h"
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#include "bcm2708_chip/mphi.h"
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#include "bcm2708_chip/usb.h"
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#ifdef __BCM2708A0__
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#include "bcm2708_chip/rng_a0.h"
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#else
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#include "bcm2708_chip/rng.h"
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#endif
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// Note: these macro evaluate argument twice - beware of side effects
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#define ALIAS_NORMAL(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x00000000)) // normal cached data (uses main 128K L2 cache)
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#define ALIAS_L1_NONALLOCATING(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x40000000)) // Doesn't allocate in L1 cache, will allocate in L2
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#if defined(__BCM2708__)
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// HW-2827 workaround
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#define ALIAS_L1L2_NONALLOCATING(x) ALIAS_L1_NONALLOCATING(x)
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#define ALIAS_L1L2_NONALLOCATING_READ(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x80000000)) // cache coherent but non-allocating in L1 and L2
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#else
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#define ALIAS_L1L2_NONALLOCATING(x) ((void*)(((unsigned)(x)&~0xc0000000)|0x80000000)) // cache coherent but non-allocating in L1 and L2
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#define ALIAS_L1L2_NONALLOCATING_READ(x) ALIAS_L1L2_NONALLOCATING(x)
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#endif
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#define ALIAS_COHERENT(x) ALIAS_L1L2_NONALLOCATING(x)
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#define ALIAS_DIRECT(x) ((void*)(((unsigned)(x)&~0xc0000000)|0xc0000000)) // uncached
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#define ALIAS_ANY_NONALLOCATING(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1L2_NONALLOCATING(x)) // eliminate L1+L2 allocation from whatever alias is supplied
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#define ALIAS_ANY_NONALLOCATING_READ(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1L2_NONALLOCATING_READ(x))
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#define ALIAS_ANY_L1_NONALLOCATING(x) (IS_ALIAS_DIRECT(x)?ALIAS_DIRECT(x):ALIAS_L1_NONALLOCATING(x)) // eliminate L1 allocation from whatever alias is supplied
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#define IS_ALIAS_NORMAL(x) ((((unsigned)(x)>>30)&0x3)==0)
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#define IS_ALIAS_L1_NONALLOCATING(x) ((((unsigned)(x)>>30)&0x3)==1)
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#if defined(__BCM2708__)
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// HW-2827 workaround
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#define IS_ALIAS_L1L2_NONALLOCATING(x) IS_ALIAS_L1_NONALLOCATING(x)
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#else
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#define IS_ALIAS_L1L2_NONALLOCATING(x) ((((unsigned)(x)>>29)&0x7)==4) // make sure we are not considering peripherals
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#endif
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#define IS_ALIAS_DIRECT(x) ((((unsigned)(x)>>30)&0x3)==3)
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#define IS_ALIAS_NONALLOCATING(x) (((unsigned)(x)>>29)>=3)
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#define IS_ALIAS_PERIPHERAL(x) (((unsigned)(x)>>29)==0x3)
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#define IS_ALIAS_COHERENT(x) IS_ALIAS_L1L2_NONALLOCATING(x)
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#define IS_ALIAS_NOT_L1(p) (IS_ALIAS_L1_NONALLOCATING(p) || IS_ALIAS_NONALLOCATING(p))
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//number of cores
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#define VIDEOCORE_NUM_CORES 2
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//The size of the stacked SDRAM
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#define SDRAM_SIZE (1024 * 1024 * 128) //32MBytes
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#define SDRAM_START_ADDRESS 0 //starts at 0 in our memory space
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//The size of the L2 cache
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#define L2CACHE_SIZE (1024 * 128) //starts at 0 in our memory space
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//default interrupt vector table base address
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#define INTERRUPT_VECTOR_BASE 0
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//common interrupts
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#define INTERRUPT_EXCEPTION_OFFSET 0
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#define INTERRUPT_EXCEPTION_NUM 32
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#define INTERRUPT_SOFTINT_OFFSET 32
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#define INTERRUPT_SOFTINT_NUM 32
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#define INTERRUPT_HARDINT_OFFSET 64
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#define INTERRUPT_HARDINT_NUM 64
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#define MAX_TIMER_NUM 4
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#define MAX_EXCEPTION_NUM 8
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// In A0 address order (ie RESET_CONTROLLER for B0 is later in the list)
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#define BOOTROM_BASE_ADDRESS 0x60000000
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#define L2CACHE_BASE L2_BASE
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#define I0CACHE_BASE L1_BASE
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#define D0CACHE_BASE (L1_BASE+0x100)
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#define SDRAM_BASE_ADDRESS SD_BASE
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#define DEBUG_MASTER_BASE NU_BASE
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#define ARBITER_CTRL_BASE SYSAC_BASE
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#define VPU0_THREAD_CTRL_BASE_ADDRESS 0x18011000
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// vc_run APB Bridge - 0x1A00_0000 - 0x1A0F_FFFF
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#define RUN_ARBITER_CTRL_BASE_ADDRESS 0x1A003000
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#define V3D_BASE_ADDRESS 0x1A005000
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#define VPU1_THREAD_CTRL_BASE_ADDRESS 0x1A008000
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#define VPU1_UNIFORM_MEM_BASE_ADDRESS 0x1A00A000
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#define V3D_MEM1_BASE_ADDRESS 0x1A00B000
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#define V3D_MEM2_BASE_ADDRESS 0x1A00C000
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#define VIDEOCODEC_BASE_ADDRESS 0x7f000000
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// peri_audio APB Bridge - 0x7e20_0000 - 0x7E21_FFFF
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#define UART_BASE_ADDRESS UART_BASE
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#define I2C_BASE_0 I2C0_BASE
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#define PIXELVALVE_0_BASE_ADDRESS PIXELVALVE0_BASE
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#define PIXELVALVE_1_BASE_ADDRESS PIXELVALVE1_BASE
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#define DSI_BASE DSI0_BASE
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#define PWM_BASE_ADDRESS PWM_BASE
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#define PERFMON_BASE_ADDRESS PRM_BASE
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// #define SPI_BASE_ADDRESS SPI_BASE
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// #define DSI1_BASE_ADDRESS DSI1_BASE
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#define OTP_BASE_ADDRESS OTP_BASE
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// #define CPG_BASE_ADDRESS CPG_BASE
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// #define TEMP_SENS_BASE_ADDRESS TS_BASE
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// cprman Audio APB bridge
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#define POWERMAN_BASE_ADDRESS PM_BASE
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#define RESET_CONTROLLER_BASE RS_BASE
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#define JPEG_BASE JP_BASE
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#define TRANSPOSER_BASE_ADDRESS TXP_BASE
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//#define CCP2TX_BASE CCP2TX_BASE // definition in ccp2tx.h
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// what to do with these ??
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#define DISPC_BASE_ADDRESS 0x1C009000
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#define CDP_BASE 0x1C00E000
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#define ACIS_BASE_ADDRESS 0x1C004800
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#define ADC_BASE_ADDRESS 0x1C00E000
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// The AXI bus to the SMI - 0x1C20_0000 - 0x1C2F_FFFF
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#define SMI_BASE 0x7E600000
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#define SMI_BASE_DIRECT 0x7E601000
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// perp run APB bridge
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// peri_image APB Bridge - 0x7e80_0000 - 0x7E81_FFFF
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// Camera - now have two Unicam modules at
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// CAM 0 : 0x7e800000 (CAM0_BASE)
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// CAM 1 : 0x7e801000 (CAM1_BASE)
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#define I2C_BASE_1 I2C1_BASE
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#define I2C_BASE_2 I2C2_BASE
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#define PIXELVALVE_2_BASE_ADDRESS PIXELVALVE2_BASE
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#define VEC_BASE_ADDRESS VEC_BASE
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//interrupt definitions
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#define INTERRUPT_HW_NUM (64)
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#define INTERRUPT_HW_OFFSET (64)
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#define INTERRUPT_SW_OFFSET (32)
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#define INTERRUPT_SW_NUM (32)
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#define INTERRUPT_TIMER0 (INTERRUPT_HW_OFFSET + 0 )
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#define INTERRUPT_TIMER1 (INTERRUPT_HW_OFFSET + 1 )
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#define INTERRUPT_TIMER2 (INTERRUPT_HW_OFFSET + 2 )
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#define INTERRUPT_TIMER3 (INTERRUPT_HW_OFFSET + 3 )
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#define INTERRUPT_CODEC0 (INTERRUPT_HW_OFFSET + 4 )
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#define INTERRUPT_CODEC1 (INTERRUPT_HW_OFFSET + 5 )
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#define INTERRUPT_CODEC2 (INTERRUPT_HW_OFFSET + 6 )
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#define INTERRUPT_JPEG (INTERRUPT_HW_OFFSET + 7 )
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#define INTERRUPT_ISP (INTERRUPT_HW_OFFSET + 8 )
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#define INTERRUPT_USB (INTERRUPT_HW_OFFSET + 9 )
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#define INTERRUPT_3D (INTERRUPT_HW_OFFSET + 10 )
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#define INTERRUPT_TRANSPOSER (INTERRUPT_HW_OFFSET + 11 )
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#define INTERRUPT_MULTICORESYNC0 (INTERRUPT_HW_OFFSET + 12 )
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#define INTERRUPT_MULTICORESYNC1 (INTERRUPT_HW_OFFSET + 13 )
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#define INTERRUPT_MULTICORESYNC2 (INTERRUPT_HW_OFFSET + 14 )
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#define INTERRUPT_MULTICORESYNC3 (INTERRUPT_HW_OFFSET + 15 )
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#define INTERRUPT_DMA0 (INTERRUPT_HW_OFFSET + 16 )
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#define INTERRUPT_DMA1 (INTERRUPT_HW_OFFSET + 17 )
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#define INTERRUPT_DMA2 (INTERRUPT_HW_OFFSET + 18 )
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#define INTERRUPT_DMA3 (INTERRUPT_HW_OFFSET + 19 )
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#define INTERRUPT_DMA4 (INTERRUPT_HW_OFFSET + 20 )
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#define INTERRUPT_DMA5 (INTERRUPT_HW_OFFSET + 21 )
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#define INTERRUPT_DMA6 (INTERRUPT_HW_OFFSET + 22 )
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#define INTERRUPT_DMA7 (INTERRUPT_HW_OFFSET + 23 )
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#define INTERRUPT_DMA8 (INTERRUPT_HW_OFFSET + 24 )
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#if defined(__BCM2708A0__)
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// A0 only has 9 dma interrupts
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//#define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
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//#define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
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//#define INTERRUPT_DMA11 (INTERRUPT_HW_OFFSET + 27 )
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//#define INTERRUPT_DMA12 (INTERRUPT_HW_OFFSET + 28 )
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//#define INTERRUPT_DMA13 (INTERRUPT_HW_OFFSET + 29 )
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//#define INTERRUPT_DMA14 (INTERRUPT_HW_OFFSET + 30 )
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//#define INTERRUPT_DMA15 (INTERRUPT_HW_OFFSET + 31 )
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#else
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#define INTERRUPT_DMA9 (INTERRUPT_HW_OFFSET + 25 )
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#define INTERRUPT_DMA10 (INTERRUPT_HW_OFFSET + 26 )
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#define INTERRUPT_DMA11_12_13_14 (INTERRUPT_HW_OFFSET + 27 )
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#define INTERRUPT_DMA_ALL (INTERRUPT_HW_OFFSET + 28 )
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#define INTERRUPT_UART_SPI0_SPI1 (INTERRUPT_HW_OFFSET + 29 )
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#define INTERRUPT_AUXIO INTERRUPT_UART_SPI0_SPI1
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#define INTERRUPT_ARM (INTERRUPT_HW_OFFSET + 30 )
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#define INTERRUPT_DMA_VPU (INTERRUPT_HW_OFFSET + 31 )
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#endif
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#define INTERRUPT_HOSTPORT (INTERRUPT_HW_OFFSET + 32 )
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#define INTERRUPT_VIDEOSCALER (INTERRUPT_HW_OFFSET + 33 )
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#define INTERRUPT_CCP2TX (INTERRUPT_HW_OFFSET + 34 )
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#define INTERRUPT_SDC (INTERRUPT_HW_OFFSET + 35 )
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#define INTERRUPT_DSI0 (INTERRUPT_HW_OFFSET + 36 )
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#define INTERRUPT_AVE (INTERRUPT_HW_OFFSET + 37 )
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#define INTERRUPT_CAM0 (INTERRUPT_HW_OFFSET + 38 )
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# define INTERRUPT_CCP2 INTERRUPT_CAM0 // backward compatibility
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#define INTERRUPT_CAM1 (INTERRUPT_HW_OFFSET + 39 )
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# define INTERRUPT_CSI2 INTERRUPT_CAM1 // backward compatibility
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#define INTERRUPT_HDMI0 (INTERRUPT_HW_OFFSET + 40 )
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#define INTERRUPT_HDMI1 (INTERRUPT_HW_OFFSET + 41 )
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#define INTERRUPT_PIXELVALVE1 (INTERRUPT_HW_OFFSET + 42 )
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#define INTERRUPT_I2C_SLV (INTERRUPT_HW_OFFSET + 43 )
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#define INTERRUPT_DSI1 (INTERRUPT_HW_OFFSET + 44 )
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#define INTERRUPT_PWA0 (INTERRUPT_HW_OFFSET + 45 )
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#define INTERRUPT_PWA1 (INTERRUPT_HW_OFFSET + 46 )
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#define INTERRUPT_CPR (INTERRUPT_HW_OFFSET + 47 )
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#define INTERRUPT_SMI (INTERRUPT_HW_OFFSET + 48 )
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#define INTERRUPT_GPIO0 (INTERRUPT_HW_OFFSET + 49 )
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#define INTERRUPT_GPIO1 (INTERRUPT_HW_OFFSET + 50 )
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#define INTERRUPT_GPIO2 (INTERRUPT_HW_OFFSET + 51 )
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#define INTERRUPT_GPIO3 (INTERRUPT_HW_OFFSET + 52 )
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#define INTERRUPT_I2C (INTERRUPT_HW_OFFSET + 53 )
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#define INTERRUPT_SPI (INTERRUPT_HW_OFFSET + 54 )
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#define INTERRUPT_I2SPCM (INTERRUPT_HW_OFFSET + 55 )
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#define INTERRUPT_SDIO (INTERRUPT_HW_OFFSET + 56 )
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#define INTERRUPT_UART (INTERRUPT_HW_OFFSET + 57 )
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#define INTERRUPT_SLIMBUS (INTERRUPT_HW_OFFSET + 58 )
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#define INTERRUPT_VEC (INTERRUPT_HW_OFFSET + 59 )
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#define INTERRUPT_CPG (INTERRUPT_HW_OFFSET + 60 )
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#define INTERRUPT_RNG (INTERRUPT_HW_OFFSET + 61 )
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#if defined(__BCM2708A0__)
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// FIXME: see middleware/rpc/rpc.c
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#define INTERRUPT_SPARE4 (INTERRUPT_HW_OFFSET + 62 )
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#define INTERRUPT_SPARE5 (INTERRUPT_HW_OFFSET + 63 )
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#else
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#define INTERRUPT_ASDIO (INTERRUPT_HW_OFFSET + 62 )
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#define INTERRUPT_AVSPMON (INTERRUPT_HW_OFFSET + 63 )
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#endif
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#define INTERRUPT_DUMMY (INTERRUPT_HW_OFFSET + 63 )
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// aliases
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#define INTERRUPT_HOSTINTERFACE INTERRUPT_HOSTPORT
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#define INTERRUPT_SDCARDHOST INTERRUPT_SDIO
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// temporary dummy register definitions to avoid compile errors
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#define DUMMYREG HW_REGISTER_RW( 0x7C ) //software exception vector 15
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/*---------------------------------------------------------------------------*/
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/* TODO FIXME ETC... VCII Clock Manager defs */
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#define CMPREC DUMMYREG
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#define CMPRE1 DUMMYREG
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#define CMPRE2 DUMMYREG
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#define CMPRE3 DUMMYREG
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#define CMPLLC DUMMYREG
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#define CMPLL1 DUMMYREG
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#define CMPLL2 DUMMYREG
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#define CMPLL3 DUMMYREG
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#define CMCORE DUMMYREG
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#define CMCAM DUMMYREG
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#define CMLCD DUMMYREG
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#define CMACIS DUMMYREG
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#define CMPCM DUMMYREG
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#define CMUSB DUMMYREG
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#define CMGEN DUMMYREG
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#define CMMSP DUMMYREG
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#define CMUART DUMMYREG
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#define CMTIMER DUMMYREG
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#define CMUARTF DUMMYREG
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#define CMTIMERF DUMMYREG
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#define CMNVT DUMMYREG
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/*---------------------------------------------------------------------------*/
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/* Nexus Controller */
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#define NOWNT HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x4)
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#define NIOREQ HW_REGISTER_RW(DEBUG_MASTER_BASE + 0x0)
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/*---------------------------------------------------------------------------*/
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/* Reset Controller */
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// #define RSTCS HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x0)
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// #define RSTWD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x4)
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// #define RSTID HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x8)
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// #define RSTFD HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0xc)
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//
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// #define RSC0ADDR HW_REGISTER_RW(RESET_CONTROLLER_BASE + 0x10)
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/*---------------------------------------------------------------------------*/
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/* Scaler hardware registers */
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#define SCALER_BASE_ADDRESS SCALER_BASE
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#define SCALER_INPUT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x00 )
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#define SCALER_IRQ_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x04 )
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#define SCALER_ID HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x08 )
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#define SCALER_ALT_CONTROL HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x0C )
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#define SCALER_PROFILE HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x10 )
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#define SCALER_DITHER HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x14 )
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//#define SCALER_DISPEOLN HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x18 )
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#define SCALER_DISP_LIST_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x20 )
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#define SCALER_DISP_LIST_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x24 )
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#define SCALER_DISP_LIST_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x28 )
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#define SCALER_DISP_LIST_STATUS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x2C )
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#define SCALER_DISPCTL_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x40 )
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#define SCALER_DISPBKGND_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x44 )
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#define SCALER_DISPSTAT_0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x48 )
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#define SCALER_DISPCTL_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x50 )
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#define SCALER_DISPBKGND_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x54 )
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#define SCALER_DISPSTAT_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x58 )
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#define SCALER_DISPBASE_1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x5C )
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#define SCALER_DISPCTL_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x60 )
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#define SCALER_DISPBKGND_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x64 )
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#define SCALER_DISPSTAT_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x68 )
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#define SCALER_DISPBASE_2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x6C )
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#define SCALER_GAM_ADDRESS HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0x78 )
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#define SCALER_GAM_DATA HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xE0 )
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//#define SCALER_DISPSLAVE0 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC0 )
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//#define SCALER_DISPSLAVE1 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xC8 )
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//#define SCALER_DISPSLAVE2 HW_REGISTER_RW( SCALER_BASE_ADDRESS + 0xD0 )
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//the start location of the scalers context memory
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#define SCALER_CONTEXT_MEMORY_START (SCALER_BASE_ADDRESS + 0x2000)
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#define SCALER_CONTEXT_MEM_SIZE ( 1024 * 16 ) //16k
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//the size of the line buffer memory
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#define SCALER_LINE_BUFFER_MEM_SIZE (94 * 1024)
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//The size of the COB buffer (the output fifo) in pixels
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#define SCALER_COB_FIFO_SIZE (0x4000) //16Kpix == 48kBytes
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/*---------------------------------------------------------------------------*/
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/* PWM */
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#define PWMCTL HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x00 )
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#define PWMSTA HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x04 )
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#define PWMDMAC HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x08 )
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#define PWMRNG1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10 )
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#define PWMDAT1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x14 )
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#define PWMFIF1 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x18 )
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#define PWMRNG2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x20 )
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#define PWMDAT2 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x24 )
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#define PWMRNG3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x30 )
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#define PWMDAT3 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x34 )
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#define PWMRNG4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x40 )
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#define PWMDAT4 HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x44 )
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#define PWMRNG(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n ) // n=1,2,3,4
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#define PWMDAT(n) HW_REGISTER_RW( PWM_BASE_ADDRESS + 0x10*n + 4 )
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#define PWMCTL_PWEN1 0
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#define PWMCTL_MODE1 1
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#define PWMCTL_RPTL1 2
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#define PWMCTL_SBIT1 3
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#define PWMCTL_POLA1 4
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#define PWMCTL_USEF1 5
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#define PWMCTL_CLRF1 6
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#define PWMCTL_MSEN1 7
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#define PWMCTL_PWEN2 8
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#define PWMCTL_MODE2 9
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#define PWMCTL_RPTL2 10
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#define PWMCTL_SBIT2 11
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#define PWMCTL_POLA2 12
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#define PWMCTL_USEF2 13
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#define PWMCTL_MSEN2 15
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#define PWMCTL_PWEN3 16
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#define PWMCTL_MODE3 17
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#define PWMCTL_RPTL3 18
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#define PWMCTL_SBIT3 19
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#define PWMCTL_POLA3 20
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#define PWMCTL_USEF3 21
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#define PWMCTL_MSEN3 23
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#define PWMCTL_PWEN4 24
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#define PWMCTL_MODE4 25
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#define PWMCTL_RPTL4 26
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#define PWMCTL_SBIT4 27
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#define PWMCTL_POLA4 28
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#define PWMCTL_USEF4 29
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#define PWMCTL_MSEN4 31
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#define PWMCTL_PWEN(n) (((n-1)<<3)+0) // n=1,2,3,4
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#define PWMCTL_MODE(n) (((n-1)<<3)+1)
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#define PWMCTL_RPTL(n) (((n-1)<<3)+2)
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#define PWMCTL_SBIT(n) (((n-1)<<3)+3)
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#define PWMCTL_POLA(n) (((n-1)<<3)+4)
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#define PWMCTL_USEF(n) (((n-1)<<3)+5)
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#define PWMCTL_MSEN(n) (((n-1)<<3)+7)
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#define PWMSTA_FULL1 0
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#define PWMSTA_EMPT1 1
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#define PWMSTA_WERR1 2
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#define PWMSTA_RERR1 3
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#define PWMSTA_GAPO1 4
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#define PWMSTA_GAPO2 5
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#define PWMSTA_GAPO3 6
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#define PWMSTA_GAPO4 7
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#define PWMSTA_BERR 8
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#define PWMSTA_STA1 9
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#define PWMSTA_STA2 10
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#define PWMSTA_STA3 11
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#define PWMSTA_STA4 12
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#define PWMDMAC_DREQ_LEN 8
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#define PWMDMAC_DREQ 0
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#define PWMDMAC_PANIC_LEN 8
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#define PWMDMAC_PANIC 8
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#define PWMDMAC_ENAB 31
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/*---------------------------------------------------------------------------*/
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/* Transposer */
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#define TRANSPOSER_DST_PTR HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x00 )
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#define TRANSPOSER_DST_PITCH HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x04 )
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#define TRANSPOSER_DIMENSIONS HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x08 )
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#define TRANSPOSER_CONTROL HW_REGISTER_RW( TRANSPOSER_BASE_ADDRESS + 0x0C )
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#define TRANSPOSER_PROGRESS HW_REGISTER_RO( TRANSPOSER_BASE_ADDRESS + 0x10 )
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/*---------------------------------------------------------------------------*/
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/* Video Codec */
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#define VCSIGNAL0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b4)
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#define VCINTMASK0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408b8)
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#define VCSIGNAL1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408bc)
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#define VCINTMASK1 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x4408c0)
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#ifndef VCODEC_VERSION
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// Set default to old A0 version
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#define VCODEC_VERSION 821
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#endif
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#if (VCODEC_VERSION>=800)
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#define VCE_BASE 0x7f100000
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#define VCE_DATA_MEM_OFFSET 0
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#define VCE_DATA_MEM_SIZE 0x2000
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#define VCE_PROGRAM_MEM_OFFSET 0x10000
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#define VCE_PROGRAM_MEM_SIZE 0x4000
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#define VCE_REGISTERS_OFFSET 0x20000
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#define VCE_REGISTERS_COUNT 63
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#define VCE_STATUS_OFFSET 0x40000
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#define VCE_STATUS_BUSYBITS_MASK 0xffff
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#define VCE_STATUS_REASON_POS 16
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#define VCE_STATUS_REASON_MASK 0x1f
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#define VCE_BUSY_BKPT 0x00
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#define VCE_BUSY_USER 0x01 // up to 0x07 inclusive
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#define VCE_BUSY_DMAIN 0x08
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#define VCE_BUSY_DMAOUT 0x09
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#define VCE_BUSY_MEMSYNC 0x0a
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#define VCE_BUSY_SLEEP 0x0b
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#define VCE_REASON_STOPPED 0x10
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#define VCE_REASON_RUNNING 0x11
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#define VCE_REASON_RESET 0x12
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#define VCE_REASON_SINGLE 0x13
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#define VCE_STATUS_RUNNING_POS 24
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#define VCE_STATUS_NANOFLAG_POS 25
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#define VCE_STATUS_INTERRUPT_POS 31
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#define VCE_VERSION_OFFSET 0x40004
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#define VCE_PC_PF0_OFFSET 0x40008
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#define VCE_PC_IF0_OFFSET 0x4000c
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#define VCE_PC_RD0_OFFSET 0x40010
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#define VCE_PC_EX0_OFFSET 0x40014
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#define VCE_CONTROL_OFFSET 0x40020
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#define VCE_CONTROL_CLEAR_RUN 0
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#define VCE_CONTROL_SET_RUN 1
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#define VCE_CONTROL_SINGLE_STEP 3
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#define VCE_BAD_ADDR_OFFSET 0x40030
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#define VCE_SEMA_CLEAR_OFFSET 0x40024
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#define VCE_SEMA_SET_OFFSET 0x40028
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#define VCE_SEMA_COUNT 8
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#define VCE_SIM_DEBUG_OPTIONS_OFFSET 0x40100
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#define VCE_DATA_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x100000)
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#define VCE_PROGRAM_MEM_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000)
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#define VCE_REGISTERS_BASE HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x120000)
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#define VCE_STATUS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140000)
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#define VCE_VERSION HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140004)
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#define VCE_PC_PF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140008)
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#define VCE_PC_IF0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x14000C)
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#define VCE_PC_RD0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140010)
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#define VCE_PC_EX0 HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140014)
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#define VCE_CONTROL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140020)
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#define VCE_SEMA_CLEAR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140024)
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#define VCE_SEMA_SET HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140028)
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#define VCE_BAD_ADDR HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140030)
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#define VCE_SIM_DEBUG_OPTIONS HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x140100)
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#else
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#define PP_PC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110000)
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#define PP_CNTL HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110004)
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#define PP_ACC HW_REGISTER_RW(VIDEOCODEC_BASE_ADDRESS + 0x110008)
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#endif
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/*---------------------------------------------------------------------------*/
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/* DSI */
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|
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// Define some macros for compatability with old VCIII code which does not
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// know about more than one dsi peripheral. Just direct it to DSI0...
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#define DSI_CTRL HW_REGISTER_RW( DSI_BASE + 0x00 )
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#define DSI_CMD_PKTC HW_REGISTER_RW( DSI_BASE + 0x04 )
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#define DSI_CMD_PKTH HW_REGISTER_RW( DSI_BASE + 0x08 )
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#define DSI_RX1_PKTH HW_REGISTER_RW( DSI_BASE + 0x0C )
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#define DSI_RX2_PKTH HW_REGISTER_RW( DSI_BASE + 0x10 )
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#define DSI_CMD_DATA_FIFO HW_REGISTER_RW( DSI_BASE + 0x14 )
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#define DSI_DISP0_CTRL HW_REGISTER_RW( DSI_BASE + 0x18 )
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#define DSI_DISP1_CTRL HW_REGISTER_RW( DSI_BASE + 0x1C )
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#define DSI_PIX_FIFO HW_REGISTER_RW( DSI_BASE + 0x20 )
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#define DSI_INT_STATUS HW_REGISTER_RW( DSI_BASE + 0x24 )
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#define DSI_INT_ENABLE HW_REGISTER_RW( DSI_BASE + 0x28 )
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#define DSI_STAT HW_REGISTER_RW( DSI_BASE + 0x2C )
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#define DSI_HSTX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x30 )
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#define DSI_LPRX_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x34 )
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#define DSI_TA_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x38 )
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#define DSI_PR_TO_CNT HW_REGISTER_RW( DSI_BASE + 0x3C )
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#define DSI_PHY_CONTROL HW_REGISTER_RW( DSI_BASE + 0x40 )
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// HSCLKZERO, HSCLKPRE, HSCLKPREP
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#define DSI_HS_CLT0 HW_REGISTER_RW( DSI_BASE + 0x44 )
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// HSCLKTRAIL, HSCLKPOST
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#define DSI_HS_CLT1 HW_REGISTER_RW( DSI_BASE + 0x48 )
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// HSWAKEUP
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#define DSI_HS_CLT2 HW_REGISTER_RW( DSI_BASE + 0x4C )
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// HS EXIT, ZERO, PRE
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#define DSI_HS_DLT3 HW_REGISTER_RW( DSI_BASE + 0x50 )
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// HS TRAIL LPX
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#define DSI_HS_DLT4 HW_REGISTER_RW( DSI_BASE + 0x54 )
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// HS INIT
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#define DSI_HS_DLT5 HW_REGISTER_RW( DSI_BASE + 0x58 )
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// lp GET SURE GO LPX
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#define DSI_LP_DLT6 HW_REGISTER_RW( DSI_BASE + 0x5C )
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// LP WAKEUP
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#define DSI_LP_DLT7 HW_REGISTER_RW( DSI_BASE + 0x60 )
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#define DSI_AFEC0 HW_REGISTER_RW( DSI_BASE + 0x64 )
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#define DSI_AFEC1 HW_REGISTER_RW( DSI_BASE + 0x68 )
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#define DSI_TST_SEL HW_REGISTER_RW( DSI_BASE + 0x6C )
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#define DSI_TST_MON HW_REGISTER_RW( DSI_BASE + 0x70 )
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|
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/*---------------------------------------------------------------------------*/
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/* CDP */
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|
|
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#define CDPC HW_REGISTER_RW( CDP_BASE + 0x00 )
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|
#define CDP_PHYC HW_REGISTER_RW( CDP_BASE + 0x04 )
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#define CDP_PHYTSTDAT HW_REGISTER_RW( CDP_BASE + 0x08 )
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|
#define CDP_DEBUG0 HW_REGISTER_RW( CDP_BASE + 0x0C )
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#define CDP_DEBUG1 HW_REGISTER_RW( CDP_BASE + 0x10 )
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|
|
/*---------------------------------------------------------------------------*/
|
|
/* BootROM Peripheral */
|
|
|
|
#define BOOTROM_ROM_START ( BOOTROM_BASE_ADDRESS + 0x0 ) //Start of the ROM
|
|
#define BOOTROM_ROM_LENGTH ( 1024 * 32 ) // Length of the Boot ROM
|
|
|
|
#define BOOTROM_RAM_START ( BOOTROM_BASE_ADDRESS + 0x8000 ) //Start of the RAM
|
|
#define BOOTROM_RAM_LENGTH ( 1024 * 2 ) // Length of the Boot RAM
|
|
|
|
#define BOOTROM_BRCTL HW_REGISTER_RW( BOOTROM_BASE_ADDRESS + 0xC000 )
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|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* Unicam Peripheral */
|
|
#define UNICAM_REG( x, d ) HW_REGISTER_RW( (((x) == 0) ? CAM0_BASE : CAM1_BASE) + d )
|
|
|
|
#if defined(__BCM2708A0__)
|
|
#define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 )
|
|
#define UNICAM_STA( x ) UNICAM_REG( x, 0x004 )
|
|
#define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 )
|
|
#define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c )
|
|
#define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 )
|
|
#define UNICAM_DAT0( x ) UNICAM_REG( x, 0x014 )
|
|
#define UNICAM_DAT1( x ) UNICAM_REG( x, 0x018 )
|
|
#define UNICAM_DAT2( x ) UNICAM_REG( x, 0x01c )
|
|
#define UNICAM_DAT3( x ) UNICAM_REG( x, 0x020 )
|
|
#define UNICAM_CMP0( x ) UNICAM_REG( x, 0x024 )
|
|
#define UNICAM_CMP1( x ) UNICAM_REG( x, 0x028 )
|
|
#define UNICAM_CAP0( x ) UNICAM_REG( x, 0x02c )
|
|
#define UNICAM_CAP1( x ) UNICAM_REG( x, 0x030 )
|
|
#define UNICAM_DBG0( x ) UNICAM_REG( x, 0x0f0 )
|
|
#define UNICAM_DBG1( x ) UNICAM_REG( x, 0x0f4 )
|
|
#define UNICAM_DBG2( x ) UNICAM_REG( x, 0x0f8 )
|
|
#define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 )
|
|
#define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 )
|
|
#define UNICAM_IDI( x ) UNICAM_REG( x, 0x108 )
|
|
#define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c )
|
|
#define UNICAM_IBSA( x ) UNICAM_REG( x, 0x110 )
|
|
#define UNICAM_IBEA( x ) UNICAM_REG( x, 0x114 )
|
|
#define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 )
|
|
#define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c )
|
|
#define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 )
|
|
#define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 )
|
|
#define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 )
|
|
#define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c )
|
|
#define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 )
|
|
#define UNICAM_DBSA( x ) UNICAM_REG( x, 0x204 )
|
|
#define UNICAM_DBEA( x ) UNICAM_REG( x, 0x208 )
|
|
#define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c )
|
|
#else
|
|
#define UNICAM_CTRL( x ) UNICAM_REG( x, 0x000 )
|
|
#define UNICAM_STA( x ) UNICAM_REG( x, 0x004 )
|
|
#define UNICAM_ANA( x ) UNICAM_REG( x, 0x008 )
|
|
#define UNICAM_PRI( x ) UNICAM_REG( x, 0x00c )
|
|
#define UNICAM_CLK( x ) UNICAM_REG( x, 0x010 )
|
|
#define UNICAM_CLT( x ) UNICAM_REG( x, 0x014 )
|
|
#define UNICAM_DAT0( x ) UNICAM_REG( x, 0x018 )
|
|
#define UNICAM_DAT1( x ) UNICAM_REG( x, 0x01c )
|
|
#define UNICAM_DAT2( x ) UNICAM_REG( x, 0x020 )
|
|
#define UNICAM_DAT3( x ) UNICAM_REG( x, 0x024 )
|
|
#define UNICAM_DLT( x ) UNICAM_REG( x, 0x028 )
|
|
#define UNICAM_CMP0( x ) UNICAM_REG( x, 0x02c )
|
|
#define UNICAM_CMP1( x ) UNICAM_REG( x, 0x030 )
|
|
#define UNICAM_CAP0( x ) UNICAM_REG( x, 0x034 )
|
|
#define UNICAM_CAP1( x ) UNICAM_REG( x, 0x038 )
|
|
#define UNICAM_ICTL( x ) UNICAM_REG( x, 0x100 )
|
|
#define UNICAM_ISTA( x ) UNICAM_REG( x, 0x104 )
|
|
#define UNICAM_IDI0( x ) UNICAM_REG( x, 0x108 )
|
|
#define UNICAM_IPIPE( x ) UNICAM_REG( x, 0x10c )
|
|
#define UNICAM_IBSA0( x ) UNICAM_REG( x, 0x110 )
|
|
#define UNICAM_IBEA0( x ) UNICAM_REG( x, 0x114 )
|
|
#define UNICAM_IBLS( x ) UNICAM_REG( x, 0x118 )
|
|
#define UNICAM_IBWP( x ) UNICAM_REG( x, 0x11c )
|
|
#define UNICAM_IHWIN( x ) UNICAM_REG( x, 0x120 )
|
|
#define UNICAM_IHSTA( x ) UNICAM_REG( x, 0x124 )
|
|
#define UNICAM_IVWIN( x ) UNICAM_REG( x, 0x128 )
|
|
#define UNICAM_IVSTA( x ) UNICAM_REG( x, 0x12c )
|
|
#define UNICAM_ICC( x ) UNICAM_REG( x, 0x130 )
|
|
#define UNICAM_ICS( x ) UNICAM_REG( x, 0x134 )
|
|
#define UNICAM_IDC( x ) UNICAM_REG( x, 0x138 )
|
|
#define UNICAM_IDPO( x ) UNICAM_REG( x, 0x13c )
|
|
#define UNICAM_IDCA( x ) UNICAM_REG( x, 0x140 )
|
|
#define UNICAM_IDCD( x ) UNICAM_REG( x, 0x144 )
|
|
#define UNICAM_IDS( x ) UNICAM_REG( x, 0x148 )
|
|
#define UNICAM_DCS( x ) UNICAM_REG( x, 0x200 )
|
|
#define UNICAM_DBSA0( x ) UNICAM_REG( x, 0x204 )
|
|
#define UNICAM_DBEA0( x ) UNICAM_REG( x, 0x208 )
|
|
#define UNICAM_DBWP( x ) UNICAM_REG( x, 0x20c )
|
|
#define UNICAM_DBCTL( x ) UNICAM_REG( x, 0x300 )
|
|
#define UNICAM_IBSA1( x ) UNICAM_REG( x, 0x304 )
|
|
#define UNICAM_IBEA1( x ) UNICAM_REG( x, 0x308 )
|
|
#define UNICAM_IDI1( x ) UNICAM_REG( x, 0x30c )
|
|
#define UNICAM_DBSA1( x ) UNICAM_REG( x, 0x310 )
|
|
#define UNICAM_DBEA1( x ) UNICAM_REG( x, 0x314 )
|
|
#define UNICAM_MISC( x ) UNICAM_REG( x, 0x400 )
|
|
#endif
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* CCP2TX Peripheral - now from ccp2tx[_a0].h */
|
|
#define CCP2TC CCP2TX_TC
|
|
#define CCP2TS CCP2TX_TS
|
|
#ifndef __BCM2708A0__
|
|
#define CCP2TAC CCP2TX_TAC
|
|
#endif
|
|
#define CCP2TPC CCP2TX_TPC
|
|
#define CCP2TSC CCP2TX_TSC
|
|
#define CCP2TIC CCP2TX_TIC
|
|
#define CCP2TTC CCP2TX_TTC
|
|
#define CCP2TBA CCP2TX_TBA
|
|
#define CCP2TDL CCP2TX_TDL
|
|
#define CCP2TD CCP2TX_TD
|
|
#ifndef __BCM2708A0__
|
|
#define CCP2TSPARE CCP2TX_TSPARE
|
|
#endif
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* VEC Peripheral */
|
|
|
|
#define WSE_RESET VEC_WSE_RESET
|
|
#define WSE_CONTROL VEC_WSE_CONTROL
|
|
#define WSE_WSS_DATA VEC_WSE_WSS_DATA
|
|
#define WSE_VPS_DATA_1 VEC_WSE_VPS_DATA_1
|
|
#define WSE_VPS_CONTROL VEC_WSE_VPS_CONTROL
|
|
|
|
#define CGMSAE_RESET VEC_CGMSAE_RESET
|
|
#define CGMSAE_TOP_CONTROL VEC_CGMSAE_TOP_CONTROL
|
|
#define CGMSAE_BOT_CONTROL VEC_CGMSAE_BOT_CONTROL
|
|
#define CGMSAE_TOP_FORMAT VEC_CGMSAE_TOP_FORMAT
|
|
#define CGMSAE_BOT_FORMAT VEC_CGMSAE_BOT_FORMAT
|
|
#define CGMSAE_TOP_DATA VEC_CGMSAE_TOP_DATA
|
|
#define CGMSAE_BOT_DATA VEC_CGMSAE_BOT_DATA
|
|
#define CGMSAE_REVID VEC_CGMSAE_REVID
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* System Timer */
|
|
|
|
// The old register names are used all over the place, so we probably need to
|
|
// keep these for now.
|
|
// These also appear in systimer.h; ideally, any modules which access these
|
|
// registers directly should #include that header file.
|
|
#if 1 // TODO: remove these one day.
|
|
#define STCS_0 ST_CS
|
|
#define STC_0 ST_CLO
|
|
#define STCLO_0 ST_CLO
|
|
#define STCHI_0 ST_CHI
|
|
#define STC0_0 ST_C0
|
|
#define STC1_0 ST_C1
|
|
#define STC2_0 ST_C2
|
|
#define STC3_0 ST_C3
|
|
|
|
#define STCS ST_CS
|
|
#define STC ST_CLO
|
|
#define STCLO ST_CLO
|
|
#define STCHI ST_CHI
|
|
#define STC0 ST_C0
|
|
#define STC1 ST_C1
|
|
#define STC2 ST_C2
|
|
#define STC3 ST_C3
|
|
#endif
|
|
/*---------------------------------------------------------------------------*/
|
|
/* Crypto/ID module */
|
|
#define IDCLVWMCU HW_REGISTER_RW(0x10002000)
|
|
#define IDCMDIDU HW_REGISTER_RW(0x10002004)
|
|
#define IDCKEYHU HW_REGISTER_RW(0x10002008)
|
|
#define IDCKEYLU HW_REGISTER_RW(0x1000200C)
|
|
#define IDCCMD HW_REGISTER_RW(0x10002010)
|
|
#define IDCCFG HW_REGISTER_RW(0x10002014)
|
|
#define IDCKSEL HW_REGISTER_RW(0x10002018)
|
|
#define IDCLVWMC HW_REGISTER_RW(0x10002020)
|
|
#define IDCMDID HW_REGISTER_RW(0x10002024)
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* Single 16550 UART */
|
|
#define URBR HW_REGISTER_RO(UART_BASE + 0x00)
|
|
#define UTHR HW_REGISTER_RW(UART_BASE + 0x00)
|
|
#define UIER HW_REGISTER_RW(UART_BASE + 0x04)
|
|
#define UIIR HW_REGISTER_RO(UART_BASE + 0x08)
|
|
#define UFCR HW_REGISTER_RW(UART_BASE + 0x08)
|
|
#define ULCR HW_REGISTER_RW(UART_BASE + 0x0C)
|
|
#define UMCR HW_REGISTER_RW(UART_BASE + 0x10)
|
|
#define ULSR HW_REGISTER_RW(UART_BASE + 0x14)
|
|
#define UMSR HW_REGISTER_RW(UART_BASE + 0x18)
|
|
#define USCR HW_REGISTER_RW(UART_BASE + 0x1C)
|
|
#define UDLL HW_REGISTER_RW(UART_BASE + 0x00)
|
|
#define UDLM HW_REGISTER_RW(UART_BASE + 0x04)
|
|
#define UEN HW_REGISTER_RW(UART_BASE + 0x20)
|
|
|
|
#define VIDEOCORE_NUM_UART_PORTS 1
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* ADC */
|
|
#define ADCCS HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x00)
|
|
#define ADCR0 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x04)
|
|
#define ADCR1 HW_REGISTER_RW(ADC_BASE_ADDRESS + 0x08)
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* General Purpose I/O */
|
|
|
|
//Max num of pins in the chip
|
|
#define GPIO_MAX_PINS 54
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* JPEG block */
|
|
#define JCTRL HW_REGISTER_RW(JPEG_BASE + 0)
|
|
#define JICST HW_REGISTER_RW(JPEG_BASE + 0x4)
|
|
#define JMCTRL HW_REGISTER_RW(JPEG_BASE + 0x8)
|
|
#define JDCCTRL HW_REGISTER_RW(JPEG_BASE + 0x0C)
|
|
#define JCBA HW_REGISTER_RW(JPEG_BASE + 0x10)
|
|
#define JNCB HW_REGISTER_RW(JPEG_BASE + 0x14)
|
|
#define JSDA HW_REGISTER_RW(JPEG_BASE + 0x18)
|
|
#define JNSB HW_REGISTER_RW(JPEG_BASE + 0x1C)
|
|
#define JSBO HW_REGISTER_RW(JPEG_BASE + 0x20)
|
|
#define JMOP HW_REGISTER_RW(JPEG_BASE + 0x24)
|
|
#define JHADDR HW_REGISTER_RW(JPEG_BASE + 0x28)
|
|
#define JHWDATA HW_REGISTER_RW(JPEG_BASE + 0x2C)
|
|
#define JMADDR HW_REGISTER_RW(JPEG_BASE + 0x30)
|
|
#define JMWDATA HW_REGISTER_RW(JPEG_BASE + 0x34)
|
|
#define JOADDR HW_REGISTER_RW(JPEG_BASE + 0x38)
|
|
#define JOWDATA HW_REGISTER_RW(JPEG_BASE + 0x3C)
|
|
#define JQADDR HW_REGISTER_RW(JPEG_BASE + 0x40)
|
|
#define JQWDATA HW_REGISTER_RW(JPEG_BASE + 0x44)
|
|
#define JQCTRL HW_REGISTER_RW(JPEG_BASE + 0x48)
|
|
#define JC0BA HW_REGISTER_RW(JPEG_BASE + 0x4C)
|
|
#define JC1BA HW_REGISTER_RW(JPEG_BASE + 0x50)
|
|
#define JC2BA HW_REGISTER_RW(JPEG_BASE + 0x54)
|
|
#define JC0S HW_REGISTER_RW(JPEG_BASE + 0x58)
|
|
#define JC1S HW_REGISTER_RW(JPEG_BASE + 0x5C)
|
|
#define JC2S HW_REGISTER_RW(JPEG_BASE + 0x60)
|
|
#define JC0W HW_REGISTER_RW(JPEG_BASE + 0x64)
|
|
#define JC1W HW_REGISTER_RW(JPEG_BASE + 0x68)
|
|
#define JC2W HW_REGISTER_RW(JPEG_BASE + 0x6C)
|
|
|
|
#define JCTRL_START (1 << 7)
|
|
#define JCTRL_DCTEN (1 << 4)
|
|
#define JCTRL_RESET (1 << 3)
|
|
#define JCTRL_FLUSH (1 << 2)
|
|
#define JCTRL_STUFF (1 << 1)
|
|
#define JCTRL_MODE (1 << 0)
|
|
|
|
#define JHADDR_TABLEF (1 << 31)
|
|
|
|
#define JICST_ERR (1 << 19)
|
|
#define JICST_MARKER (1 << 18)
|
|
#define JICST_SDONE (1 << 17)
|
|
#define JICST_CDONE (1 << 16)
|
|
#define JICST_INTE (1 << 3)
|
|
#define JICST_INTM (1 << 2)
|
|
#define JICST_INTSD (1 << 1)
|
|
#define JICST_INTCD (1 << 0)
|
|
|
|
#define JDCCTRL_DISDC (1 << 20)
|
|
#define JDCCTRL_SETDC(n) (1 << ((n) + 16))
|
|
#define JDCCTRL_DCCOMP_MASK 0xFFFF
|
|
|
|
#define JMCTRL_DC_TAB(n) (1 << (2*(n)))
|
|
#define JMCTRL_AC_TAB(n) (1 << (2*(n)+1))
|
|
#define JMCTRL_NUMCMP (1 << 8)
|
|
#define JMCTRL_CMP(n) (1 << (4*(n) + 16))
|
|
#define JMCTRL_420_MODE (0 << 14)
|
|
#define JMCTRL_422_MODE (1 << 14)
|
|
#define JMCTRL_444_MODE (2 << 14)
|
|
|
|
#define JMCTRL_UNUSED_BITS ((1 << 13) | (1 << 12) | (1 << 11))
|
|
|
|
#define AC_HUFFTABLE_OFFSET(t) ((t) * 0x100)
|
|
#define DC_HUFFTABLE_OFFSET(t) ((t) * 0x10 + 0x200)
|
|
|
|
#define AC_OSETTABLE_OFFSET(t) ((t) * 0x10)
|
|
#define DC_OSETTABLE_OFFSET(t) ((t) * 0x10 + 0x20)
|
|
|
|
#define AC_MAXCTABLE_OFFSET(t) ((t) * 0x10)
|
|
#define DC_MAXCTABLE_OFFSET(t) ((t) * 0x10 + 0x20)
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* External Memory Interface */
|
|
#define SDCS HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x00)
|
|
#define SDSA HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x04)
|
|
#define SDSB HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x08)
|
|
#define SDSC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x0C)
|
|
#define SDEM HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x10)
|
|
#define SDPT HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x14)
|
|
#define SDIDL HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x18)
|
|
#define SDRTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x1C)
|
|
#define SDWTC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x20)
|
|
#define SDRDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x24)
|
|
#define SDWDC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x28)
|
|
#define SDRAC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x2C)
|
|
#define SDCYC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x30)
|
|
#define SDACC HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x34)
|
|
#define SDDAT HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x38)
|
|
#define SDSECSRT0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x3C)
|
|
#define SDSECEND0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x40)
|
|
#define SDSECSRT1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x44)
|
|
#define SDSECEND1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x48)
|
|
#define SDSECSRT2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x4C)
|
|
#define SDSECEND2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x50)
|
|
#define SDSECSRT3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x54)
|
|
#define SDSECEND3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x58)
|
|
#define SDDELC0 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x5C)
|
|
#define SDDELS0 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x60)
|
|
#define SDDELC1 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x64)
|
|
#define SDDELS1 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x68)
|
|
#define SDDELC2 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x6C)
|
|
#define SDDELS2 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x70)
|
|
#define SDDELC3 HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x74)
|
|
#define SDDELS3 HW_REGISTER_RO( SDRAM_BASE_ADDRESS + 0x78)
|
|
#define SDTMC HW_REGISTER_RW( SDRAM_BASE_ADDRESS + 0x7C)
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* Secondary Memory Interface */
|
|
|
|
#define SMICS HW_REGISTER_RW(SMI_BASE + 0x00)
|
|
#define SMIL HW_REGISTER_RW(SMI_BASE + 0x04)
|
|
#define SMIA HW_REGISTER_RW(SMI_BASE + 0x08)
|
|
#define SMID HW_REGISTER_RW(SMI_BASE + 0x0C)
|
|
#define SMIDSR0 HW_REGISTER_RW(SMI_BASE + 0x10)
|
|
#define SMIDSW0 HW_REGISTER_RW(SMI_BASE + 0x14)
|
|
#define SMIDSR1 HW_REGISTER_RW(SMI_BASE + 0x18)
|
|
#define SMIDSW1 HW_REGISTER_RW(SMI_BASE + 0x1C)
|
|
#define SMIDSR2 HW_REGISTER_RW(SMI_BASE + 0x20)
|
|
#define SMIDSW2 HW_REGISTER_RW(SMI_BASE + 0x24)
|
|
#define SMIDSR3 HW_REGISTER_RW(SMI_BASE + 0x28)
|
|
#define SMIDSW3 HW_REGISTER_RW(SMI_BASE + 0x2C)
|
|
#define SMIDC HW_REGISTER_RW(SMI_BASE + 0x30)
|
|
#define SMIDCS HW_REGISTER_RW(SMI_BASE + 0x34)
|
|
#define SMIDA HW_REGISTER_RW(SMI_BASE + 0x38)
|
|
#define SMIDD HW_REGISTER_RW(SMI_BASE + 0x3C)
|
|
#define SMIFD HW_REGISTER_RW(SMI_BASE + 0x40)
|
|
|
|
#define SMI_FIFO_ADDRESS(device,addr) (((((device))&0x3)<<8)|((addr)&0xff))
|
|
|
|
// SMI control register bits
|
|
#define SMICS_ENABLE 0
|
|
#define SMICS_DONE 1
|
|
#define SMICS_ACTIVE 2
|
|
#define SMICS_START 3
|
|
#define SMICS_CLEARFIFO 4
|
|
#define SMICS_WRITE 5
|
|
#define SMICS_PAD 6
|
|
#define SMICS_TEEN 8
|
|
#define SMICS_INTD 9
|
|
#define SMICS_INTT 10
|
|
#define SMICS_INTR 11
|
|
#define SMICS_PVMODE 12
|
|
#define SMICS_SETERR 13
|
|
#define SMICS_PXLDAT 14
|
|
#define SMICS_EDREQ 15
|
|
#define SMICS_AFERR 25
|
|
#define SMICS_TXW 26
|
|
#define SMICS_RXR 27
|
|
#define SMICS_TXD 28
|
|
#define SMICS_RXD 29
|
|
#define SMICS_TXE 30
|
|
#define SMICS_RXF 31
|
|
|
|
// SMI address and direct address register bits.
|
|
#define SMIA_DEVICE 8
|
|
#define SMIDA_DEVICE 8
|
|
|
|
// SMI DSR* and DSW* common fields
|
|
#define SMIDS_STROBE 0
|
|
#define SMIDS_DREQ 7
|
|
#define SMIDS_PACE 8
|
|
#define SMIDS_PACEALL 15
|
|
#define SMIDS_HOLD 16
|
|
#define SMIDS_SETUP 24
|
|
#define SMIDS_WIDTH 30
|
|
// SMI DSR* register specific
|
|
#define SMIDS_FSETUP 22
|
|
#define SMIDS_MODE68 23
|
|
// SMI DSW* register specific
|
|
#define SMIDS_SWAP 22
|
|
#define SMIDS_FORMAT 23
|
|
|
|
// SMI direct control/status register bits.
|
|
#define SMIDCS_ENABLE 0
|
|
#define SMIDCS_START 1
|
|
#define SMIDCS_DONE 2
|
|
#define SMIDCS_WRITE 3
|
|
|
|
// SMI dma control threshold register bits.
|
|
#define SMIDC_REQW 0
|
|
#define SMIDC_REQR 6
|
|
#define SMIDC_PANICW 12
|
|
#define SMIDC_PANICR 18
|
|
#define SMIDC_DMAP 24
|
|
#define SMIDC_DMAEN 28
|
|
|
|
// SMI FIFO debug
|
|
#define SMIFD_FCNT 0
|
|
#define SMIFD_FLVL 8
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* AC'97/I2S Controller */
|
|
#define ACISCS HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x00 )
|
|
#define ACISFIFO HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x04 )
|
|
#define ACISCA HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x08 )
|
|
#define ACISCD HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x0C )
|
|
#define ACISMODE HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x10 )
|
|
#define ACISASR HW_REGISTER_RW( ACIS_BASE_ADDRESS + 0x14 )
|
|
|
|
#define ACPLAYRATE 0x2c
|
|
#define ACRECORDRATE 0x32
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* SLIMbus interface */
|
|
#define SLIM_NUM_DCC 10 /* there are 10 data channel controllers */
|
|
#define SLIM_DCC_BASE(n) (SLIM_BASE + 0x200 + (n) * 0x20)
|
|
#define SLIM_DCC_PA0(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x00)
|
|
#define SLIM_DCC_PA1(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x04)
|
|
#define SLIM_DCC_CON(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x08)
|
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#define SLIM_DCC_STAT(n) HW_REGISTER_RW(SLIM_DCC_BASE(n) + 0x0c)
|
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|
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#if defined(__BCM2708A0__)
|
|
// backward compatibility for drivers that use B0 register definitions
|
|
#define SLIM_MC_IN_CON SLIM_SMC_IN_CON
|
|
#define SLIM_MC_OUT_CON SLIM_SMC_OUT_CON
|
|
#define SLIM_MC_IN_STAT SLIM_SMC_IN_STAT
|
|
#define SLIM_MC_OUT_STAT SLIM_SMC_OUT_STAT
|
|
#define SLIM_DMA_MC_TX SLIM_DMA_SMC_TX
|
|
#define SLIM_DMA_MC_RX SLIM_DMA_SMC_RX
|
|
#endif
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* USB Peripheral */
|
|
#define USB_DIEPINT_off(n) HW_REGISTER_RW(&USB_DIEPINT+(n*0x20))
|
|
#define USB_HCINT_off(n) HW_REGISTER_RW(&USB_HCINT+(n*0x20))
|
|
|
|
#define USB_DFIFOn(n) HW_REGISTER_RW(USB_BASE+0x1000+(n*0x1000))
|
|
#define USB_DIEPCTLn(n) HW_REGISTER_RW(USB_BASE+0x0900+(n*0x20))
|
|
#define USB_DIEPTSIZn(n) HW_REGISTER_RW(USB_BASE+0x0910+(n*0x20))
|
|
#define USB_DIEPDMAn(n) HW_REGISTER_RW(USB_BASE+0x0914+(n*0x20))
|
|
#define USB_DTXFSTSn(n) HW_REGISTER_RW(USB_BASE+0x0918+(n*0x20))
|
|
|
|
#define USB_MDIO_CSR HW_REGISTER_RW( USB_BASE + 0x80 )
|
|
#define USB_MDIO_GEN HW_REGISTER_RW( USB_BASE + 0x84 )
|
|
#define USB_VBUS_DRV HW_REGISTER_RW( USB_BASE + 0x88 )
|
|
#define USB_VBUS_DRV_SESSEND (1<<0)
|
|
#define USB_VBUS_DRV_VBUSVALID (1<<1)
|
|
#define USB_VBUS_DRV_BVALID (1<<2)
|
|
#define USB_VBUS_DRV_AVALID (1<<3)
|
|
#define USB_VBUS_DRV_DRVVBUS (1<<4)
|
|
#define USB_VBUS_DRV_CHRGVBUS (1<<5)
|
|
#define USB_VBUS_DRV_DISCHRGVBUS (1<<6)
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* PCM Controller */
|
|
#define PCMCS PCM_CS_A
|
|
//#define PCMFIFO PCM_FIFO_A erroneously defined as _RO in bcm2708_chip/pcm.h
|
|
#define PCMFIFO HW_REGISTER_RW( PCM_BASE + 0x04 )
|
|
#define PCMMODE PCM_MODE_A
|
|
#define PCMRXC PCM_RXC_A
|
|
#define PCMTXC PCM_TXC_A
|
|
#define PCMDREQ HW_REGISTER_RW( PCM_BASE + 0x14 )
|
|
#define PCMINTEN HW_REGISTER_RW( PCM_BASE + 0x18 )
|
|
#define PCMINTSTC HW_REGISTER_RW( PCM_BASE + 0x1c )
|
|
|
|
|
|
// bit fields for PCMCS
|
|
#define PCMCS_EN (1 << 0)
|
|
#define PCMCS_RXON (1 << 1)
|
|
#define PCMCS_TXON (1 << 2)
|
|
#define PCMCS_TXCLR (1 << 3)
|
|
#define PCMCS_RXCLR (1 << 4)
|
|
#define PCMCS_TXTHR_LSB 5
|
|
#define PCMCS_TXTHR_EMPTY (0 << PCMCS_TXTHR_LSB)
|
|
#define PCMCS_TXTHR_1_QUARTER (1 << PCMCS_TXTHR_LSB)
|
|
#define PCMCS_TXTHR_3_QUARTER (2 << PCMCS_TXTHR_LSB)
|
|
#define PCMCS_TXTHR_FULL (3 << PCMCS_TXTHR_LSB)
|
|
#define PCMCS_RXTHR_LSB 7
|
|
#define PCMCS_RXTHR_EMPTY (0 << PCMCS_RXTHR_LSB)
|
|
#define PCMCS_RXTHR_1_QUARTER (1 << PCMCS_RXTHR_LSB)
|
|
#define PCMCS_RXTHR_3_QUARTER (2 << PCMCS_RXTHR_LSB)
|
|
#define PCMCS_RXTHR_FULL (3 << PCMCS_RXTHR_LSB)
|
|
|
|
#define PCMCS_DMAEN (1 << 9)
|
|
#define PCMCS_INTT (1 << 10)
|
|
#define PCMCS_INTR (1 << 11)
|
|
#define PCMCS_INTE (1 << 12)
|
|
#define PCMCS_TXSYNC (1 << 13)
|
|
#define PCMCS_RXSYNC (1 << 14)
|
|
#define PCMCS_TXERR (1 << 15)
|
|
#define PCMCS_RXERR (1 << 16)
|
|
#define PCMCS_TXW (1 << 17)
|
|
#define PCMCS_RXR (1 << 18)
|
|
#define PCMCS_TXD (1 << 19)
|
|
#define PCMCS_RXD (1 << 20)
|
|
#define PCMCS_TXE (1 << 21)
|
|
#define PCMCS_RXF (1 << 22)
|
|
#define PCMCS_RXSEX (1 << 23)
|
|
#define PCMCS_SYNC (1 << 24)
|
|
|
|
// bit fields for PCMMODE
|
|
#define PCMMODE_FSI (1 << 20)
|
|
#define PCMMODE_FSM (1 << 21)
|
|
#define PCMMODE_CLKI (1 << 22)
|
|
#define PCMMODE_CLKM (1 << 23)
|
|
#define PCMMODE_FLEN 10
|
|
#define PCMMODE_FSLEN 0
|
|
#define PCMMODE_FTXP (1 << 24)
|
|
#define PCMMODE_FRXP (1 << 25)
|
|
#define PCMMODE_PDMRX (1 << 26)
|
|
#define PCMMODE_PDMRXN (1 << 27)
|
|
|
|
// macros for PCMTXC and PCMRXC
|
|
#define PCM_CH1POS_LSB 20
|
|
#define PCM_CH1WID_LSB 16
|
|
#define PCM_CH2POS_LSB 4
|
|
#define PCM_CH2WID_LSB 0
|
|
// parameters --> bitmasks
|
|
#define PCM_CH1WEX (1 << 31)
|
|
#define PCM_CH2WEX (1 << 15)
|
|
#define PCM_WIDTH2(x) ( (((x - 8) & 0x0f) << PCM_CH2WID_LSB) + PCM_CH2WEX * (((x-8)&0x10)>>4) )
|
|
#define PCM_POS2(x) (((x) & 0x3ff) << PCM_CH2POS_LSB)
|
|
#define PCM_WIDTH1(x) ( (((x - 8) & 0x0f) << PCM_CH1WID_LSB) + PCM_CH1WEX * (((x-8)&0x10)>>4) )
|
|
#define PCM_POS1(x) (((x) & 0x3ff) << PCM_CH1POS_LSB)
|
|
#define PCM_CH2EN (1 << 14)
|
|
#define PCM_CH1EN (1 << 30)
|
|
// bitmasks --> parameters
|
|
#define PCM_WID1(x) ( (((x >> PCM_CH1WID_LSB) & 0x0f) + 8) + ((x & PCM_CH1WEX) ? 16 : 0) )
|
|
#define PCM_WID2(x) ( (((x >> PCM_CH2WID_LSB) & 0x0f) + 8) + ((x & PCM_CH2WEX) ? 16 : 0) )
|
|
|
|
// bit fields in the PCMDREQ register
|
|
#define PCMDREQ_TXPANICTHR_LSB 24
|
|
#define PCMDREQ_RXPANICTHR_LSB 16
|
|
#define PCMDREQ_TXDREQTHR_LSB 8
|
|
#define PCMDREQ_RXDREQTHR_LSB 0
|
|
|
|
#define PCM_FIFO_DEPTH 64 // words
|
|
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* I2C Master */
|
|
#define I2CC_0 HW_REGISTER_RW(I2C_BASE_0 + 0x00)
|
|
#define I2CS_0 HW_REGISTER_RW(I2C_BASE_0 + 0x04)
|
|
#define I2CDLEN_0 HW_REGISTER_RW(I2C_BASE_0 + 0x08)
|
|
#define I2CA_0 HW_REGISTER_RW(I2C_BASE_0 + 0x0C)
|
|
#define I2CFIFO_0 HW_REGISTER_RW(I2C_BASE_0 + 0x10)
|
|
#define I2CDIV_0 HW_REGISTER_RW(I2C_BASE_0 + 0x14)
|
|
#define I2CDEL_0 HW_REGISTER_RW(I2C_BASE_0 + 0x18)
|
|
#define I2CCLKT_0 HW_REGISTER_RW(I2C_BASE_0 + 0x1C)
|
|
|
|
#define I2CC_1 HW_REGISTER_RW(I2C_BASE_1 + 0x00)
|
|
#define I2CS_1 HW_REGISTER_RW(I2C_BASE_1 + 0x04)
|
|
#define I2CDLEN_1 HW_REGISTER_RW(I2C_BASE_1 + 0x08)
|
|
#define I2CA_1 HW_REGISTER_RW(I2C_BASE_1 + 0x0C)
|
|
#define I2CFIFO_1 HW_REGISTER_RW(I2C_BASE_1 + 0x10)
|
|
#define I2CDIV_1 HW_REGISTER_RW(I2C_BASE_1 + 0x14)
|
|
#define I2CDEL_1 HW_REGISTER_RW(I2C_BASE_1 + 0x18)
|
|
#define I2CCLKT_1 HW_REGISTER_RW(I2C_BASE_1 + 0x1C)
|
|
|
|
#define I2CC_2 HW_REGISTER_RW(I2C_BASE_2 + 0x00)
|
|
#define I2CS_2 HW_REGISTER_RW(I2C_BASE_2 + 0x04)
|
|
#define I2CDLEN_2 HW_REGISTER_RW(I2C_BASE_2 + 0x08)
|
|
#define I2CA_2 HW_REGISTER_RW(I2C_BASE_2 + 0x0C)
|
|
#define I2CFIFO_2 HW_REGISTER_RW(I2C_BASE_2 + 0x10)
|
|
#define I2CDIV_2 HW_REGISTER_RW(I2C_BASE_2 + 0x14)
|
|
#define I2CDEL_2 HW_REGISTER_RW(I2C_BASE_2 + 0x18)
|
|
#define I2CCLKT_2 HW_REGISTER_RW(I2C_BASE_2 + 0x1C)
|
|
|
|
#define I2CC_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x00 )
|
|
#define I2CS_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x04 )
|
|
#define I2CDLEN_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x08 )
|
|
#define I2CA_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x0C )
|
|
#define I2CFIFO_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x10 )
|
|
#define I2CDIV_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x14 )
|
|
#define I2CDEL_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x18 )
|
|
#define I2CCLKT_x( x ) HW_REGISTER_RW( ((0 == x) ? I2C_BASE_0 : (I2C_BASE_1 + (0x1000 * (x-1)))) + 0x1C )
|
|
|
|
// define some bitfields within these I2C registers...
|
|
#define I2CC_EN (1 << 15)
|
|
#define I2CC_INTR (1 << 10)
|
|
#define I2CC_INTT (1 << 9)
|
|
#define I2CC_INTD (1 << 8)
|
|
#define I2CC_START (1 << 7)
|
|
#define I2CC_CLEAR (3 << 4)
|
|
#define I2CC_READ (1 << 0)
|
|
|
|
#define I2CS_CLKT (1 << 9)
|
|
#define I2CS_ERR (1 << 8)
|
|
#define I2CS_RXF (1 << 7)
|
|
#define I2CS_TXE (1 << 6)
|
|
#define I2CS_RXD (1 << 5)
|
|
#define I2CS_TXD (1 << 4)
|
|
#define I2CS_RXR (1 << 3)
|
|
#define I2CS_TXW (1 << 2)
|
|
#define I2CS_DONE (1 << 1)
|
|
#define I2CS_TA (1 << 0)
|
|
|
|
#define I2CDEL_FEDL (16)
|
|
#define I2CDEL_REDL (0)
|
|
|
|
//Note! Remove this eventually.
|
|
//Just define the old VCII I2C peripheral
|
|
#define I2CC I2CC_0
|
|
#define I2CS I2CS_0
|
|
#define I2CDLEN I2CDLEN_0
|
|
#define I2CA I2CA_0
|
|
#define I2CFIFO I2CFIFO_0
|
|
#define I2CDIV I2CDIV_0
|
|
#define I2CDEL I2CDEL_0
|
|
#define I2CCLKT I2CCLKT_0
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* Performance Monitor */
|
|
#define PRMCS HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x00)
|
|
#define PRMCV HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x04)
|
|
#define PRMSCC HW_REGISTER_RW(PERFMON_BASE_ADDRESS + 0x08)
|
|
|
|
/*---------------------------------------------------------------------------*/
|
|
/* OTP */
|
|
|
|
//#define OTP_CONFIG_REG OTP_WRAP_CONFIG_REG
|
|
//OTP bit definitions
|
|
// NB the addressing has changed between VCIII and VCIV - we now address by row (each row contains 32 bits)
|
|
#define OTP_JTAG_DEBUG_KEY_ROW 8
|
|
#define OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS 4
|
|
#define OTP_VPU_CACHE_KEY_ROW (OTP_JTAG_DEBUG_KEY_ROW+OTP_JTAG_DEBUG_KEY_SIZE_IN_ROWS)
|
|
#define OTP_VPU_CACHE_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_CONTROL_ROW (OTP_VPU_CACHE_KEY_ROW+OTP_VPU_CACHE_KEY_SIZE_IN_ROWS)
|
|
#define OTP_CONTROL_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_BOOT_ROM_ROW (OTP_CONTROL_ROW+OTP_CONTROL_SIZE_IN_ROWS)
|
|
#define OTP_BOOT_ROM_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_BOOT_ROM_ROW_REDUNDANT (OTP_BOOT_ROM_ROW+OTP_BOOT_ROM_SIZE_IN_ROWS)
|
|
|
|
#ifdef __BCM2708A0__
|
|
#define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS)
|
|
#define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS)
|
|
#define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS)
|
|
#define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS)
|
|
#define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS)
|
|
#define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS)
|
|
#define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS)
|
|
#define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS)
|
|
#define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS)
|
|
#define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS)
|
|
#define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS)
|
|
#define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1
|
|
|
|
// Suspend/resume secure RAM key: ensure that these values match the ones
|
|
// used in vcsuspend_asm_vc4.s
|
|
#define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 64
|
|
#define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2
|
|
|
|
// to allow A0 to continue to build without too many #ifdefs define the redundant rows to be the same as the original
|
|
#define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT OTP_BOOT_SIGNING_KEY_ROW
|
|
#define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT OTP_CODE_SIGNING_KEY_ROW
|
|
#define OTP_HDCP_AES_KEY_ROW_REDUNDANT OTP_HDCP_AES_KEY_ROW
|
|
#define OTP_PUBLIC_KEY_ROW_REDUNDANT OTP_PUBLIC_KEY_ROW
|
|
#define OTP_PRIVATE_KEY_ROW_REDUNDANT OTP_PRIVATE_KEY_ROW
|
|
#else
|
|
// BCM2708B0 has less reliable OTP so we need a redundant row for the boot signing key (and the corresponding parity)
|
|
#define OTP_BOOT_SIGNING_KEY_ROW (OTP_BOOT_ROM_ROW_REDUNDANT+OTP_BOOT_ROM_SIZE_IN_ROWS) // 19
|
|
#define OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT (OTP_BOOT_SIGNING_KEY_ROW+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 23
|
|
|
|
#define OTP_BOOT_SIGNING_PARITY_ROW (OTP_BOOT_SIGNING_KEY_ROW_REDUNDANT+OTP_BOOT_SIGNING_KEY_SIZE_IN_ROWS) // 27
|
|
#define OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_CODE_SIGNING_KEY_ROW (OTP_BOOT_SIGNING_PARITY_ROW+OTP_BOOT_SIGNING_PARITY_SIZE_IN_ROWS) // 28
|
|
#define OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_CODE_SIGNING_KEY_ROW_REDUNDANT (OTP_CODE_SIGNING_KEY_ROW+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 32
|
|
|
|
#define OTP_CODE_SIGNING_PARITY_ROW (OTP_CODE_SIGNING_KEY_ROW_REDUNDANT+OTP_CODE_SIGNING_KEY_SIZE_IN_ROWS) // 36
|
|
#define OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_HDCP_AES_KEY_ROW (OTP_CODE_SIGNING_PARITY_ROW+OTP_CODE_SIGNING_PARITY_SIZE_IN_ROWS) // 37
|
|
#define OTP_HDCP_AES_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_HDCP_AES_KEY_ROW_REDUNDANT (OTP_HDCP_AES_KEY_ROW+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 41
|
|
|
|
#define OTP_HDCP_AES_PARITY_ROW (OTP_HDCP_AES_KEY_ROW_REDUNDANT+OTP_HDCP_AES_KEY_SIZE_IN_ROWS) // 45
|
|
#define OTP_HDCP_AES_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_PUBLIC_KEY_ROW (OTP_HDCP_AES_PARITY_ROW+OTP_HDCP_AES_PARITY_SIZE_IN_ROWS) // 46
|
|
#define OTP_PUBLIC_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_PUBLIC_KEY_ROW_REDUNDANT (OTP_PUBLIC_KEY_ROW+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 50
|
|
|
|
#define OTP_PUBLIC_PARITY_ROW (OTP_PUBLIC_KEY_ROW_REDUNDANT+OTP_PUBLIC_KEY_SIZE_IN_ROWS) // 54
|
|
#define OTP_PUBLIC_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_PRIVATE_KEY_ROW (OTP_PUBLIC_PARITY_ROW+OTP_PUBLIC_PARITY_SIZE_IN_ROWS) // 55
|
|
#define OTP_PRIVATE_KEY_SIZE_IN_ROWS 4
|
|
|
|
#define OTP_PRIVATE_KEY_ROW_REDUNDANT (OTP_PRIVATE_KEY_ROW+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 59
|
|
|
|
#define OTP_PRIVATE_PARITY_ROW (OTP_PRIVATE_KEY_ROW_REDUNDANT+OTP_PRIVATE_KEY_SIZE_IN_ROWS) // 63
|
|
#define OTP_PRIVATE_PARITY_SIZE_IN_ROWS 1
|
|
|
|
#define OTP_CODE_SIGNING_FLAG_ROW (OTP_PRIVATE_PARITY_ROW+OTP_PRIVATE_PARITY_SIZE_IN_ROWS) // 64
|
|
#define OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS 1
|
|
|
|
// Suspend/resume secure RAM key: ensure that these values match the ones
|
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// used in vcsuspend_asm_vc4.s
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#define OTP_SUSPEND_SECURE_RAM_KEY (OTP_CODE_SIGNING_FLAG_ROW+OTP_CODE_SIGNING_FLAG_SIZE_IN_ROWS) // 65
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#define OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS 2
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// strictly this is C0 only
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#define OTP_BOOT_EXTRAS_ROW (OTP_SUSPEND_SECURE_RAM_KEY+OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS) // 67
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#define OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS 1
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// locations fixed by hardware
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#define OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT 68
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#define OTP_VPU_CACHE_KEY_ROW_REDUNDANT 72
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#define OTP_JTAG_VPU_PARITY_REDUNDANT 76
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#if( OTP_BOOT_EXTRAS_ROW+OTP_BOOT_EXTRAS_ROW_SIZE_IN_ROWS > OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT )
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#error "User OTP space has overwritten CPU bits" OTP_SUSPEND_SECURE_RAM_KEY OTP_SUSPEND_SECURE_RAM_KEY_SIZE_IN_ROWS OTP_JTAG_DEBUG_KEY_ROW_REDUNDANT
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#endif
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#endif
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#define OTP_MIN_ROW OTP_JTAG_DEBUG_KEY_ROW
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#define OTP_MAX_ROW OTP_SUSPEND_SECURE_RAM_KEY
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// bit locations in the CONTROL OTP register
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#define OTP_JTAG_DEBUG_KEY_PARITY_START_BIT 0
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#define OTP_VPU_CACHE_KEY_PARITY_START_BIT 8
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#define OTP_JTAG_DISABLE_BIT 16
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#define OTP_JTAG_DISABLE_REDUNDANT_BIT 17
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#define OTP_MACROVISION_START_BIT 18
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#define OTP_MACROVISION_REDUNDANT_START_BIT 20
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#define OTP_DECRYPTION_ENABLE_FOR_DEBUG 22
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#define OTP_ARM_DISABLE_BIT 24
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#define OTP_ARM_DISABLE_REDUNDANT_BIT 25
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#define OTP_JTAG_PARITY_MASK 0xFF
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#define OTP_VPU_CACHE_PARITY_MASK 0xFF
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#define OTP_BYTES_PER_ROW 4
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// make sure locations used by the hardware are correct
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#if( OTP_CONTROL_ROW != 16)
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#error "The OTP control row has moved - it must be 16!"
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#endif
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#if( OTP_BOOT_ROM_ROW != 17 )
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#error "The OTP bootrom row has moved - it must be 17!"
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#endif
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#if( OTP_BOOT_ROM_ROW_REDUNDANT != 18 )
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#error "The OTP bootrom copy row has moved - it must be 18!"
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#endif
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/*---------------------------------------------------------------------------*/
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/* Threading unit */
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/* Registers for the threading unit */
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#define TH0_BASE 0x18011000
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#define TH0_ADDR_MASK 0x0000003F
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#define TH1_BASE 0x1A008000
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#define TH1_ADDR_MASK 0x0000003F
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#define TH0CS HW_REGISTER_RW(TH0_BASE + 0x00)
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#define TH0CFG HW_REGISTER_RW(TH0_BASE + 0x04)
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#define TH0STPC HW_REGISTER_RW(TH0_BASE + 0x08)
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#define TH0ITPC HW_REGISTER_RW(TH0_BASE + 0x0C)
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#define TH0T0PC HW_REGISTER_RW(TH0_BASE + 0x10)
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#define TH0T0UD HW_REGISTER_RW(TH0_BASE + 0x14)
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#define TH0T1PC HW_REGISTER_RW(TH0_BASE + 0x18)
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#define TH0T1UD HW_REGISTER_RW(TH0_BASE + 0x1C)
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#define TH0T2PC HW_REGISTER_RW(TH0_BASE + 0x20)
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#define TH0T2UD HW_REGISTER_RW(TH0_BASE + 0x24)
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#define TH0T3PC HW_REGISTER_RW(TH0_BASE + 0x28)
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#define TH0T3UD HW_REGISTER_RW(TH0_BASE + 0x2C)
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#define TH1CS HW_REGISTER_RW(TH1_BASE + 0x00)
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#define TH1CFG HW_REGISTER_RW(TH1_BASE + 0x04)
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#define TH1STPC HW_REGISTER_RW(TH1_BASE + 0x08)
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#define TH1ITPC HW_REGISTER_RW(TH1_BASE + 0x0C)
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#define TH1T0PC HW_REGISTER_RW(TH1_BASE + 0x10)
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#define TH1T0UD HW_REGISTER_RW(TH1_BASE + 0x14)
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#define TH1T1PC HW_REGISTER_RW(TH1_BASE + 0x18)
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#define TH1T1UD HW_REGISTER_RW(TH1_BASE + 0x1C)
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#define TH1T2PC HW_REGISTER_RW(TH1_BASE + 0x20)
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#define TH1T2UD HW_REGISTER_RW(TH1_BASE + 0x24)
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#define TH1T3PC HW_REGISTER_RW(TH1_BASE + 0x28)
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#define TH1T3UD HW_REGISTER_RW(TH1_BASE + 0x2C)
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/* Windows Open GL plugin - emulator only */
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#define WOGLPTR HW_REGISTER_RW(0x1C00FFFC)
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/* Hardware 3D unit */
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#define GR_VCACHE_BASE 0x1a00a000
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#define GR_VCACHE_ADDR_MASK 0x00001fff
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#define GR_VCACHE_SIZE 0x00002000 // in bytes
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#define GR_UNIFORM_BASE 0x1a00c000
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#define GR_UNIFORM_ADDR_MASK 0x00000fff
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#define GR_UNIFORM_SIZE 0x00001000 // in bytes
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/* Registers for Vertex Cache Manager */
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#define GR_VCM_BASE 0x1A005C00
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#define GR_VCM_ADDR_MASK 0x0000003f
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#define GR_VCM_CI_BASE 0x1A005C80
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#define GR_VCM_CI_ADDR_MASK 0x0000007f
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#define GRMCS HW_REGISTER_RW(GR_VCM_BASE + 0x00)
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#define GRMCFG HW_REGISTER_RW(GR_VCM_BASE + 0x04)
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#define GRMSVI HW_REGISTER_RW(GR_VCM_BASE + 0x08)
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#define GRMSADR HW_REGISTER_RW(GR_VCM_BASE + 0x0C)
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#define GRMSCT HW_REGISTER_RW(GR_VCM_BASE + 0x10)
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#define GRMOADR HW_REGISTER_RW(GR_VCM_BASE + 0x14)
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#define GRMOCT HW_REGISTER_RW(GR_VCM_BASE + 0x18)
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#define GRMMCT HW_REGISTER_RW(GR_VCM_BASE + 0x1C)
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#define GRMSSI0 HW_REGISTER_RW(GR_VCM_BASE + 0x20)
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#define GRMSSI1 HW_REGISTER_RW(GR_VCM_BASE + 0x24)
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#define GRMCCT HW_REGISTER_RW(GR_VCM_BASE + 0x28)
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#define GRMCIL0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x00)
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#define GRMCIL1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x20)
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#define GRMCIH0 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x40)
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#define GRMCIH1 HW_REGISTER_RW(GR_VCM_CI_BASE + 0x60)
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#define GR_VCD_BASE 0x1A005A00
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#define GR_VCD_ADDR_MASK 0x0000007f
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#define GRDCS HW_REGISTER_RW(GR_VCD_BASE + 0x00)
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#define GRDCFG HW_REGISTER_RW(GR_VCD_BASE + 0x04)
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#define GRDACFG0 HW_REGISTER_RW(GR_VCD_BASE + 0x20)
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#define GRDACFG1 HW_REGISTER_RW(GR_VCD_BASE + 0x24)
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#define GRDACFG2 HW_REGISTER_RW(GR_VCD_BASE + 0x28)
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#define GRDACFG3 HW_REGISTER_RW(GR_VCD_BASE + 0x2C)
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#define GRDACFG4 HW_REGISTER_RW(GR_VCD_BASE + 0x30)
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#define GRDACFG5 HW_REGISTER_RW(GR_VCD_BASE + 0x34)
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#define GRDACFG6 HW_REGISTER_RW(GR_VCD_BASE + 0x38)
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#define GRDACFG7 HW_REGISTER_RW(GR_VCD_BASE + 0x3C)
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#define GRDAADR0 HW_REGISTER_RW(GR_VCD_BASE + 0x40)
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#define GRDAADR1 HW_REGISTER_RW(GR_VCD_BASE + 0x44)
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#define GRDAADR2 HW_REGISTER_RW(GR_VCD_BASE + 0x48)
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#define GRDAADR3 HW_REGISTER_RW(GR_VCD_BASE + 0x4C)
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#define GRDAADR4 HW_REGISTER_RW(GR_VCD_BASE + 0x50)
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#define GRDAADR5 HW_REGISTER_RW(GR_VCD_BASE + 0x54)
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#define GRDAADR6 HW_REGISTER_RW(GR_VCD_BASE + 0x58)
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#define GRDAADR7 HW_REGISTER_RW(GR_VCD_BASE + 0x5C)
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/* Registers for Primitive Setup Engine */
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#define GR_PSE_BASE 0x1A005800
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#define GR_PSE_ADDR_MASK 0x0000007f
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#define GRSCS HW_REGISTER_RW(GR_PSE_BASE + 0x00)
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#define GRSCFG HW_REGISTER_RW(GR_PSE_BASE + 0x04)
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#define GRSVADR HW_REGISTER_RW(GR_PSE_BASE + 0x08)
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#define GRSVFMT HW_REGISTER_RW(GR_PSE_BASE + 0x0C)
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#define GRSSP HW_REGISTER_RW(GR_PSE_BASE + 0x10)
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#define GRSPADR HW_REGISTER_RW(GR_PSE_BASE + 0x14)
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#define GRSPCT HW_REGISTER_RW(GR_PSE_BASE + 0x18)
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#define GRSAADR HW_REGISTER_RW(GR_PSE_BASE + 0x1C)
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#define GRSACT HW_REGISTER_RW(GR_PSE_BASE + 0x20)
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#define GRSDOF HW_REGISTER_RW(GR_PSE_BASE + 0x24)
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#define GRSDOU HW_REGISTER_RW(GR_PSE_BASE + 0x28)
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#define GRSDMIN HW_REGISTER_RW(GR_PSE_BASE + 0x2C)
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#define GRSDMAX HW_REGISTER_RW(GR_PSE_BASE + 0x30)
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#define GRSPSZ HW_REGISTER_RW(GR_PSE_BASE + 0x34)
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#define GRSLW HW_REGISTER_RW(GR_PSE_BASE + 0x38)
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#define GRSFSF HW_REGISTER_RW(GR_PSE_BASE + 0x3C)
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#define GRSDZS HW_REGISTER_RW(GR_PSE_BASE + 0x40)
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#define GRSHPX HW_REGISTER_RW(GR_PSE_BASE + 0x44)
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/* Debug Registers for Primitive Setup Engine */
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#define GR_PSE_DEBUG_BASE 0x1A005900
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#define GR_PSE_DEBUG_ADDR_MASK 0x00000003
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#define GRS_DBGE HW_REGISTER_RW(GR_PSE_DEBUG_BASE + 0x00)
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/* Registers for Pixel Pipeline */
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#define GR_PPL_BASE 0x1A005600
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#define GR_PPL_ADDR_MASK 0x0000007F
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#define GRPCS HW_REGISTER_RW(GR_PPL_BASE + 0x00)
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#define GRPCFG HW_REGISTER_RW(GR_PPL_BASE + 0x04)
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#define GRPCLXY HW_REGISTER_RW(GR_PPL_BASE + 0x08)
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#define GRPCLSZ HW_REGISTER_RW(GR_PPL_BASE + 0x0C)
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#define GRPVORG HW_REGISTER_RW(GR_PPL_BASE + 0x10)
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// gap of 8 bytes
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// gap of 16 bytes
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// gap of 16 bytes
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#define GRPZBCG HW_REGISTER_RW(GR_PPL_BASE + 0x40)
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#define GRPSFCG HW_REGISTER_RW(GR_PPL_BASE + 0x44)
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#define GRPSBCG HW_REGISTER_RW(GR_PPL_BASE + 0x48)
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#define GRPSCC HW_REGISTER_RW(GR_PPL_BASE + 0x4C)
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#define GRPBCFG HW_REGISTER_RW(GR_PPL_BASE + 0x50)
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#define GRPBCC HW_REGISTER_RW(GR_PPL_BASE + 0x54)
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#define GRPCDSM HW_REGISTER_RW(GR_PPL_BASE + 0x58) // xxx dc4
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#define GRPCZSM HW_REGISTER_RW(GR_PPL_BASE + 0x58)
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#define GRPCBS HW_REGISTER_RW(GR_PPL_BASE + 0x5C)
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#define GRPABS HW_REGISTER_RW(GR_PPL_BASE + 0x60)
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#define GRPFCOL HW_REGISTER_RW(GR_PPL_BASE + 0x64)
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/* Debug Registers for Pixel Pipeline */
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#define GR_PPL_DEBUG_BASE 0x1A005740
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#define GR_PPL_DEBUG_ADDR_MASK 0x0000001F
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#define GRP_FDBGO HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x00)
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#define GRP_FDBGB HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x04)
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#define GRP_FDBGR HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x08)
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#define GRP_FDBGS HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x0C)
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#define GRP_SDBG0 HW_REGISTER_RW(GR_PPL_DEBUG_BASE + 0x10)
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/* Registers for the Frame Buffer Cache */
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#define GR_FBC_BASE 0x1A005400
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#define GR_FBC_ADDR_MASK 0x0000007F
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#define GRFCS HW_REGISTER_RW(GR_FBC_BASE + 0x00)
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#define GRFCFG HW_REGISTER_RW(GR_FBC_BASE + 0x04)
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#define GRFTLOC HW_REGISTER_RW(GR_FBC_BASE + 0x08)
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#define GRFDIMS HW_REGISTER_RW(GR_FBC_BASE + 0x0C)
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#define GRFCCFG HW_REGISTER_RW(GR_FBC_BASE + 0x10)
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#define GRFCBA HW_REGISTER_RW(GR_FBC_BASE + 0x14)
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#define GRFZCFG HW_REGISTER_RW(GR_FBC_BASE + 0x1C)
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#define GRFZBA HW_REGISTER_RW(GR_FBC_BASE + 0x20)
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#define GRFZCV HW_REGISTER_RW(GR_FBC_BASE + 0x24)
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#define GRFSCV HW_REGISTER_RW(GR_FBC_BASE + 0x28)
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#define GRFCMSK HW_REGISTER_RW(GR_FBC_BASE + 0x2C)
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#define GRFECFG HW_REGISTER_RW(GR_FBC_BASE + 0x30)
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#define GRFEBA HW_REGISTER_RW(GR_FBC_BASE + 0x34)
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#define GRFCCV0 HW_REGISTER_RW(GR_FBC_BASE + 0x40)
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#define GRFCCV1 HW_REGISTER_RW(GR_FBC_BASE + 0x44)
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#define GRFCCV2 HW_REGISTER_RW(GR_FBC_BASE + 0x48)
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#define GRFCCV3 HW_REGISTER_RW(GR_FBC_BASE + 0x4C)
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#define GRFCCV4 HW_REGISTER_RW(GR_FBC_BASE + 0x50)
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#define GRFCCV5 HW_REGISTER_RW(GR_FBC_BASE + 0x54)
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#define GRFCCV6 HW_REGISTER_RW(GR_FBC_BASE + 0x58)
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#define GRFCCV7 HW_REGISTER_RW(GR_FBC_BASE + 0x5C)
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#define GR_FBC_DEBUG_BASE 0x1A005500
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#define GR_FBC_DEBUG_ADDR_MASK 0x7F
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#define GRFCSTAT HW_REGISTER_RW(GR_FBC_DEBUG_BASE + 0x00)
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/* VPM access via VRF configuration */
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#define GR_VPM_VRFCFG_BASE 0x1A005D00
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#define GR_VPM_VRFCFG_ADDR_MASK 0x00000003
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#define GRVVSTRD HW_REGISTER_RW(GR_VPM_VRFCFG_BASE + 0x00)
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/* Registers for the Texture Unit */
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/* Mipmap pointer memoies (TU0 & TU1) */
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#define GRTMPM0_BASE 0x1A005E00
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#define GRTMPM1_BASE 0x1A005F00
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#define GRTMPM0 HW_REGISTER_RW(GRTMPM0_BASE + 0x00)
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#define GRTMPM1 HW_REGISTER_RW(GRTMPM1_BASE + 0x00)
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#define GRTMPM_MASK 0xFFFFFF00
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#define GR_TU_BASE0 0x1A005200
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#define GR_TU_BASE1 0x1A005220
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#define GR_TU_BASE2 0x1A005240
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#define GR_TU_BASE3 0x1A005260
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#define GR_TU_BASE4 0x1A005280
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#define GR_TU_BASE5 0x1A0052A0
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#define GR_TU_BASE6 0x1A0052C0
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#define GR_TU_BASE7 0x1A0052E0
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#define GR_TU_DBG_BASE 0x1A005300
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#define GR_TU_ADDR_MASK 0x000000FF
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#define GR_TU_UNIT_MASK 0xFFFFFF1F
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/* Control/Status registers for TU0 & TU1 */
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#define GRTCS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x00)
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#define GRTCS1 HW_REGISTER_RW(GR_TU_BASE4 + 0x00)
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/* Common palette for all contexts per texutre unit */
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#define GRTPTBA0 HW_REGISTER_RW(GR_TU_BASE1 + 0x00)
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#define GRTPTBA1 HW_REGISTER_RW(GR_TU_BASE5 + 0x00)
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/* 4 sets of context registers for physical texture unit 0 */
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#define GRTCFG0 HW_REGISTER_RW(GR_TU_BASE0 + 0x04)
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#define GRTDIM0 HW_REGISTER_RW(GR_TU_BASE0 + 0x08)
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#define GRTBCOL0 HW_REGISTER_RW(GR_TU_BASE0 + 0x0C)
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#define GRTLBIAS0 HW_REGISTER_RW(GR_TU_BASE0 + 0x1C)
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#define GRTCFG1 HW_REGISTER_RW(GR_TU_BASE1 + 0x04)
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#define GRTDIM1 HW_REGISTER_RW(GR_TU_BASE1 + 0x08)
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#define GRTBCOL1 HW_REGISTER_RW(GR_TU_BASE1 + 0x0C)
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#define GRTLBIAS1 HW_REGISTER_RW(GR_TU_BASE1 + 0x1C)
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#define GRTCFG2 HW_REGISTER_RW(GR_TU_BASE2 + 0x04)
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#define GRTDIM2 HW_REGISTER_RW(GR_TU_BASE2 + 0x08)
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#define GRTBCOL2 HW_REGISTER_RW(GR_TU_BASE2 + 0x0C)
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#define GRTLBIAS2 HW_REGISTER_RW(GR_TU_BASE2 + 0x1C)
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#define GRTCFG3 HW_REGISTER_RW(GR_TU_BASE3 + 0x04)
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|
#define GRTDIM3 HW_REGISTER_RW(GR_TU_BASE3 + 0x08)
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|
#define GRTBCOL3 HW_REGISTER_RW(GR_TU_BASE3 + 0x0C)
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|
#define GRTLBIAS3 HW_REGISTER_RW(GR_TU_BASE3 + 0x1C)
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|
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/* 4 sets of context registers for physical texture unit 1 */
|
|
#define GRTCFG4 HW_REGISTER_RW(GR_TU_BASE4 + 0x04)
|
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#define GRTDIM4 HW_REGISTER_RW(GR_TU_BASE4 + 0x08)
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#define GRTBCOL4 HW_REGISTER_RW(GR_TU_BASE4 + 0x0C)
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#define GRTLBIAS4 HW_REGISTER_RW(GR_TU_BASE4 + 0x1C)
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|
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#define GRTCFG5 HW_REGISTER_RW(GR_TU_BASE5 + 0x04)
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#define GRTDIM5 HW_REGISTER_RW(GR_TU_BASE5 + 0x08)
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#define GRTBCOL5 HW_REGISTER_RW(GR_TU_BASE5 + 0x0C)
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#define GRTLBIAS5 HW_REGISTER_RW(GR_TU_BASE5 + 0x1C)
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#define GRTCFG6 HW_REGISTER_RW(GR_TU_BASE6 + 0x04)
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#define GRTDIM6 HW_REGISTER_RW(GR_TU_BASE6 + 0x08)
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#define GRTBCOL6 HW_REGISTER_RW(GR_TU_BASE6 + 0x0C)
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#define GRTLBIAS6 HW_REGISTER_RW(GR_TU_BASE6 + 0x1C)
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#define GRTCFG7 HW_REGISTER_RW(GR_TU_BASE7 + 0x04)
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#define GRTDIM7 HW_REGISTER_RW(GR_TU_BASE7 + 0x08)
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#define GRTBCOL7 HW_REGISTER_RW(GR_TU_BASE7 + 0x0C)
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#define GRTLBIAS7 HW_REGISTER_RW(GR_TU_BASE7 + 0x1C)
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/* TU debug registers */
|
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#define GRTDBG0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x00)
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|
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/* Extra registers per TU for child image support */
|
|
#define GRTCOFF0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x04)
|
|
#define GRTCDIM0 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x08)
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|
#define GRTCOFF1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x84)
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|
#define GRTCDIM1 HW_REGISTER_RW(GR_TU_DBG_BASE + 0x88)
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|
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/* System Registers */
|
|
#define GR_SYSTEM_BASE 0x1A005000
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|
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#define GROCS HW_REGISTER_RW(GR_SYSTEM_BASE)
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#define GROCFG HW_REGISTER_RW(GR_SYSTEM_BASE + 4)
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#define GROIDC HW_REGISTER_RW(GR_SYSTEM_BASE + 8)
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/* System debug register */
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#define GR_SYSTEM_DEBUG_BASE 0x1A005100
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#define GRODBGA HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x000)
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/* Performance Counters Regs */
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#define GROPCTRC HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x070)
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#define GROPCTRE HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x074)
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#define GROPCTR0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x080)
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#define GROPCTRS0 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x084)
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#define GROPCTR1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x088)
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#define GROPCTRS1 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x08C)
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#define GROPCTR2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x090)
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#define GROPCTRS2 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x094)
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#define GROPCTR3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x098)
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#define GROPCTRS3 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x09C)
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#define GROPCTR4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A0)
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#define GROPCTRS4 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A4)
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#define GROPCTR5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0A8)
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#define GROPCTRS5 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0AC)
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#define GROPCTR6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B0)
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#define GROPCTRS6 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B4)
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#define GROPCTR7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0B8)
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#define GROPCTRS7 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0BC)
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#define GROPCTR8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C0)
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#define GROPCTRS8 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C4)
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#define GROPCTR9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0C8)
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#define GROPCTRS9 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0CC)
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#define GROPCTR10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D0)
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#define GROPCTRS10 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D4)
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#define GROPCTR11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0D8)
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#define GROPCTRS11 HW_REGISTER_RW(GR_SYSTEM_DEBUG_BASE + 0x0DC)
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/* Performance Counters Defs */
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#define GROPCTR_FOVCULLEDPRIMS 0x01
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#define GROPCTR_FOVCLIPPEDPRIMS 0x02
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#define GROPCTR_REVCULLEDPRIMS 0x03
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#define GROPCTR_NOFEPIXELPRIMS 0x04
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#define GROPCTR_FEVALIDPRIMS 0x05
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#define GROPCTR_FEZCULLEDQUADS 0x06
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#define GROPCTR_FEVALIDQUADS 0x07
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#define GROPCTR_FEINVALIDPIXELS 0x08
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#define GROPCTR_FEPEZRDY 0x09
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#define GROPCTR_FEPEZIDLE 0x0A
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#define GROPCTR_FESTALLPREFETCH 0x0B
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#define GROPCTR_FESPMRDY 0x0C
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#define GROPCTR_FESPMSTALL 0x0D
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#define GROPCTR_TU0_SAME_SET_STALL 0x0E
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#define GROPCTR_TU0_SAME_BANK_STALL 0x0F
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#define GROPCTR_TU0_AXI_REQ_FIFO_FULL 0x10
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#define GROPCTR_TU0_CACHE_ACCESSES 0x11
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#define GROPCTR_TU0_CACHE_STALLS 0x12
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#define GROPCTR_TU0_CACHE_REQ_STALLS 0x13
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#define GROPCTR_TU0_CACHE_MISSES 0x14
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#define GROPCTR_TU0_CACHE_RCV_WAITS 0x15
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#define GROPCTR_TU1_SAME_SET_STALL 0x16
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#define GROPCTR_TU1_SAME_BANK_STALL 0x17
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#define GROPCTR_TU1_AXI_REQ_FIFO_FULL 0x18
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#define GROPCTR_TU1_CACHE_ACCESSES 0x19
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#define GROPCTR_TU1_CACHE_STALLS 0x1A
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#define GROPCTR_TU1_CACHE_REQ_STALLS 0x1B
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#define GROPCTR_TU1_CACHE_MISSES 0x1C
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#define GROPCTR_TU1_CACHE_RCV_WAITS 0x1D
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#define GROPCTR_PBE_FE_STALLS 0x1E
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#define GROPCTR_PBE_DEPTH_TEST_FAIL 0x1F
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#define GROPCTR_PBE_STCL_TEST_FAIL 0x20
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#define GROPCTR_PBE_DPTH_STCL_PASS 0x21
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#define GROPCTR_FBC_CZ_CLRFLG_FETCHES 0x22
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#define GROPCTR_FBC_CZ_LINE_FLUSHES 0x23
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#define GROPCTR_FBC_CZ_PBE_REQS 0x24
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#define GROPCTR_FBC_CZ_PBE_STALLS 0x25
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#define GROPCTR_FBC_CZ_PBE_MISSES 0x26
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#define GROPCTR_FBC_CZ_PBE_HITS 0x27
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#define GROPCTR_FBC_CZ_FETCH_STALLS 0x28
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#define GROPCTR_FBC_CZ_FE_QUAD_REQS 0x29
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#define GROPCTR_FBC_CZ_FE_LINE_REQS 0x2A
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#define GROPCTR_FBC_CZ_FE_UNUSED 0x2B
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#define GROPCTR_FBC_CZ_FE_MISSES 0x2C
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#define GROPCTR_FBC_CZ_FE_HITS 0x2D
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#define GROPCTR_FBC_CZ_FE_DISCARDED 0x2E
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#define GROPCTR_FBC_CZ_UM_STALLS 0x2F
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#define GROPCTR_FBC_CZ_FETCHES 0x30
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#define GROPCTR_FBC_CZ_EVICTIONS 0x31
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#define GROPCTR_FBC_EZ_CLRFLG_FETCHES 0x32
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#define GROPCTR_FBC_EZ_LINE_FLUSHES 0x33
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#define GROPCTR_FBC_EZ_PBE_REQS 0x34
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#define GROPCTR_FBC_EZ_PBE_STALLS 0x35
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#define GROPCTR_FBC_EZ_PBE_MISSES 0x36
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#define GROPCTR_FBC_EZ_PBE_HITS 0x37
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#define GROPCTR_FBC_EZ_FETCH_STALLS 0x38
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#define GROPCTR_FBC_EZ_FE_REQS 0x39
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#define GROPCTR_FBC_EZ_FE_MISSES 0x3A
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#define GROPCTR_FBC_EZ_FE_HITS 0x3B
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#define GROPCTR_FBC_EZ_FE_FETCHES 0x3C
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#define GROPCTR_FBC_EZ_UM_STALLS 0x3D
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#define GROPCTR_FBC_EZ_FETCHES 0x3E
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#define GROPCTR_FBC_EZ_EVICTIONS 0x3F
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//VRF defines
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#define VRF_SIZE (4096+64+64)
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#endif /* _HARDWARE_VC4_H */
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