141 lines
11 KiB
C
Executable File
141 lines
11 KiB
C
Executable File
// This file was generated by the create_regs script
|
|
#define VEC_BASE 0x7e806000
|
|
#define VEC_REVID HW_REGISTER_RW( 0x7e806100 )
|
|
#define VEC_REVID_MASK 0xffffffff
|
|
#define VEC_REVID_WIDTH 32
|
|
#define VEC_CONFIG0 HW_REGISTER_RW( 0x7e806104 )
|
|
#define VEC_CONFIG0_MASK 0xffffffff
|
|
#define VEC_CONFIG0_WIDTH 32
|
|
#define VEC_SCHPH HW_REGISTER_RW( 0x7e806108 )
|
|
#define VEC_SCHPH_MASK 0xffffffff
|
|
#define VEC_SCHPH_WIDTH 32
|
|
#define VEC_SOFT_RESET HW_REGISTER_RW( 0x7e80610c )
|
|
#define VEC_SOFT_RESET_MASK 0xffffffff
|
|
#define VEC_SOFT_RESET_WIDTH 32
|
|
#define VEC_CPS01_CPS23 HW_REGISTER_RW( 0x7e806120 )
|
|
#define VEC_CPS01_CPS23_MASK 0xffffffff
|
|
#define VEC_CPS01_CPS23_WIDTH 32
|
|
#define VEC_CPS45_CPS67 HW_REGISTER_RW( 0x7e806124 )
|
|
#define VEC_CPS45_CPS67_MASK 0xffffffff
|
|
#define VEC_CPS45_CPS67_WIDTH 32
|
|
#define VEC_CPS89_CPS1011 HW_REGISTER_RW( 0x7e806128 )
|
|
#define VEC_CPS89_CPS1011_MASK 0xffffffff
|
|
#define VEC_CPS89_CPS1011_WIDTH 32
|
|
#define VEC_CPS1213_CPS1415 HW_REGISTER_RW( 0x7e80612c )
|
|
#define VEC_CPS1213_CPS1415_MASK 0xffffffff
|
|
#define VEC_CPS1213_CPS1415_WIDTH 32
|
|
#define VEC_CPS1617_CPS1819 HW_REGISTER_RW( 0x7e806130 )
|
|
#define VEC_CPS1617_CPS1819_MASK 0xffffffff
|
|
#define VEC_CPS1617_CPS1819_WIDTH 32
|
|
#define VEC_CPS2021_CPS2223 HW_REGISTER_RW( 0x7e806134 )
|
|
#define VEC_CPS2021_CPS2223_MASK 0xffffffff
|
|
#define VEC_CPS2021_CPS2223_WIDTH 32
|
|
#define VEC_CPS2425_CPS2627 HW_REGISTER_RW( 0x7e806138 )
|
|
#define VEC_CPS2425_CPS2627_MASK 0xffffffff
|
|
#define VEC_CPS2425_CPS2627_WIDTH 32
|
|
#define VEC_CPS2829_CPS3031 HW_REGISTER_RW( 0x7e80613c )
|
|
#define VEC_CPS2829_CPS3031_MASK 0xffffffff
|
|
#define VEC_CPS2829_CPS3031_WIDTH 32
|
|
#define VEC_CPS32_CPC HW_REGISTER_RW( 0x7e806140 )
|
|
#define VEC_CPS32_CPC_MASK 0xffffffff
|
|
#define VEC_CPS32_CPC_WIDTH 32
|
|
#define VEC_CLMP0_START HW_REGISTER_RW( 0x7e806144 )
|
|
#define VEC_CLMP0_START_MASK 0xffffffff
|
|
#define VEC_CLMP0_START_WIDTH 32
|
|
#define VEC_CLMP0_END HW_REGISTER_RW( 0x7e806148 )
|
|
#define VEC_CLMP0_END_MASK 0xffffffff
|
|
#define VEC_CLMP0_END_WIDTH 32
|
|
#define VEC_FREQ3_2 HW_REGISTER_RW( 0x7e806180 )
|
|
#define VEC_FREQ3_2_MASK 0xffffffff
|
|
#define VEC_FREQ3_2_WIDTH 32
|
|
#define VEC_FREQ1_0 HW_REGISTER_RW( 0x7e806184 )
|
|
#define VEC_FREQ1_0_MASK 0xffffffff
|
|
#define VEC_FREQ1_0_WIDTH 32
|
|
#define VEC_CONFIG1 HW_REGISTER_RW( 0x7e806188 )
|
|
#define VEC_CONFIG1_MASK 0xffffffff
|
|
#define VEC_CONFIG1_WIDTH 32
|
|
#define VEC_CONFIG2 HW_REGISTER_RW( 0x7e80618c )
|
|
#define VEC_CONFIG2_MASK 0xffffffff
|
|
#define VEC_CONFIG2_WIDTH 32
|
|
#define VEC_INTERRUPT_CONTROL HW_REGISTER_RW( 0x7e806190 )
|
|
#define VEC_INTERRUPT_CONTROL_MASK 0xffffffff
|
|
#define VEC_INTERRUPT_CONTROL_WIDTH 32
|
|
#define VEC_INTERRUPT_STATUS HW_REGISTER_RW( 0x7e806194 )
|
|
#define VEC_INTERRUPT_STATUS_MASK 0xffffffff
|
|
#define VEC_INTERRUPT_STATUS_WIDTH 32
|
|
#define VEC_FCW_SECAM_B HW_REGISTER_RW( 0x7e806198 )
|
|
#define VEC_FCW_SECAM_B_MASK 0xffffffff
|
|
#define VEC_FCW_SECAM_B_WIDTH 32
|
|
#define VEC_SECAM_GAIN_VAL HW_REGISTER_RW( 0x7e80619c )
|
|
#define VEC_SECAM_GAIN_VAL_MASK 0xffffffff
|
|
#define VEC_SECAM_GAIN_VAL_WIDTH 32
|
|
#define VEC_CONFIG3 HW_REGISTER_RW( 0x7e8061a0 )
|
|
#define VEC_CONFIG3_MASK 0xffffffff
|
|
#define VEC_CONFIG3_WIDTH 32
|
|
#define VEC_CONFIG4 HW_REGISTER_RW( 0x7e8061a4 )
|
|
#define VEC_CONFIG4_MASK 0xffffffff
|
|
#define VEC_CONFIG4_WIDTH 32
|
|
#define VEC_STATUS0 HW_REGISTER_RW( 0x7e806200 )
|
|
#define VEC_STATUS0_MASK 0xffffffff
|
|
#define VEC_STATUS0_WIDTH 32
|
|
#define VEC_MASK0 HW_REGISTER_RW( 0x7e806204 )
|
|
#define VEC_MASK0_MASK 0xffffffff
|
|
#define VEC_MASK0_WIDTH 32
|
|
#define VEC_CFG HW_REGISTER_RW( 0x7e806208 )
|
|
#define VEC_CFG_MASK 0xffffffff
|
|
#define VEC_CFG_WIDTH 32
|
|
#define VEC_DAC_TEST HW_REGISTER_RW( 0x7e80620c )
|
|
#define VEC_DAC_TEST_MASK 0xffffffff
|
|
#define VEC_DAC_TEST_WIDTH 32
|
|
#define VEC_DAC_CONFIG HW_REGISTER_RW( 0x7e806210 )
|
|
#define VEC_DAC_CONFIG_MASK 0xffffffff
|
|
#define VEC_DAC_CONFIG_WIDTH 32
|
|
#define VEC_DAC_MISC HW_REGISTER_RW( 0x7e806214 )
|
|
#define VEC_DAC_MISC_MASK 0xffffffff
|
|
#define VEC_DAC_MISC_WIDTH 32
|
|
#define VEC_WSE_RESET HW_REGISTER_RW( 0x7e8060c0 )
|
|
#define VEC_WSE_RESET_MASK 0xffffffff
|
|
#define VEC_WSE_RESET_WIDTH 32
|
|
#define VEC_WSE_CONTROL HW_REGISTER_RW( 0x7e8060c4 )
|
|
#define VEC_WSE_CONTROL_MASK 0xffffffff
|
|
#define VEC_WSE_CONTROL_WIDTH 32
|
|
#define VEC_WSE_WSS_DATA HW_REGISTER_RW( 0x7e8060c8 )
|
|
#define VEC_WSE_WSS_DATA_MASK 0xffffffff
|
|
#define VEC_WSE_WSS_DATA_WIDTH 32
|
|
#define VEC_WSE_VPS_DATA_1 HW_REGISTER_RW( 0x7e8060cc )
|
|
#define VEC_WSE_VPS_DATA_1_MASK 0xffffffff
|
|
#define VEC_WSE_VPS_DATA_1_WIDTH 32
|
|
#define VEC_WSE_VPS_CONTROL HW_REGISTER_RW( 0x7e8060d0 )
|
|
#define VEC_WSE_VPS_CONTROL_MASK 0xffffffff
|
|
#define VEC_WSE_VPS_CONTROL_WIDTH 32
|
|
#define VEC_CGMSAE_TOP_CONTROL HW_REGISTER_RW( 0x7e806044 )
|
|
#define VEC_CGMSAE_TOP_CONTROL_MASK 0xffffffff
|
|
#define VEC_CGMSAE_TOP_CONTROL_WIDTH 32
|
|
#define VEC_CGMSAE_RESET HW_REGISTER_RW( 0x7e806040 )
|
|
#define VEC_CGMSAE_RESET_MASK 0xffffffff
|
|
#define VEC_CGMSAE_RESET_WIDTH 32
|
|
#define VEC_CGMSAE_BOT_CONTROL HW_REGISTER_RW( 0x7e806048 )
|
|
#define VEC_CGMSAE_BOT_CONTROL_MASK 0xffffffff
|
|
#define VEC_CGMSAE_BOT_CONTROL_WIDTH 32
|
|
#define VEC_CGMSAE_TOP_FORMAT HW_REGISTER_RW( 0x7e80604c )
|
|
#define VEC_CGMSAE_TOP_FORMAT_MASK 0xffffffff
|
|
#define VEC_CGMSAE_TOP_FORMAT_WIDTH 32
|
|
#define VEC_CGMSAE_BOT_FORMAT HW_REGISTER_RW( 0x7e806050 )
|
|
#define VEC_CGMSAE_BOT_FORMAT_MASK 0xffffffff
|
|
#define VEC_CGMSAE_BOT_FORMAT_WIDTH 32
|
|
#define VEC_CGMSAE_TOP_DATA HW_REGISTER_RW( 0x7e806054 )
|
|
#define VEC_CGMSAE_TOP_DATA_MASK 0xffffffff
|
|
#define VEC_CGMSAE_TOP_DATA_WIDTH 32
|
|
#define VEC_CGMSAE_BOT_DATA HW_REGISTER_RW( 0x7e806058 )
|
|
#define VEC_CGMSAE_BOT_DATA_MASK 0xffffffff
|
|
#define VEC_CGMSAE_BOT_DATA_WIDTH 32
|
|
#define VEC_CGMSAE_REVID HW_REGISTER_RW( 0x7e80605c )
|
|
#define VEC_CGMSAE_REVID_MASK 0xffffffff
|
|
#define VEC_CGMSAE_REVID_WIDTH 32
|
|
#define VEC_ENC_RevID HW_REGISTER_RW( 0x7e806060 )
|
|
#define VEC_ENC_RevID_MASK 0xffffffff
|
|
#define VEC_ENC_RevID_WIDTH 32
|
|
#define VEC_ENC_PrimaryControl HW_REGISTER_RW( 0x7e806068 )
|
|
#define VEC_ENC_PrimaryControl_MASK 0xffffffff
|
|
#define VEC_ENC_PrimaryControl_WIDTH 32
|