132 lines
10 KiB
C
Executable File
132 lines
10 KiB
C
Executable File
// This file was generated by the create_regs script
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#define CAM0_BASE 0x7e800000
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#define CAM0_APB_ID 0x7563616d
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#define CAM0_CTL HW_REGISTER_RW( 0x7e800000 )
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#define CAM0_CTL_MASK 0xffffffff
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#define CAM0_CTL_WIDTH 32
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#define CAM0_CTL_RESET 0000000000
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#define CAM0_STA HW_REGISTER_RW( 0x7e800004 )
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#define CAM0_STA_MASK 0xffffffff
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#define CAM0_STA_WIDTH 32
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#define CAM0_STA_RESET 0000000000
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#define CAM0_ANA HW_REGISTER_RW( 0x7e800008 )
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#define CAM0_ANA_MASK 0xffffffff
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#define CAM0_ANA_WIDTH 32
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#define CAM0_ANA_RESET 0000000000
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#define CAM0_PRI HW_REGISTER_RW( 0x7e80000c )
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#define CAM0_PRI_MASK 0xffffffff
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#define CAM0_PRI_WIDTH 32
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#define CAM0_PRI_RESET 0000000000
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#define CAM0_CLK HW_REGISTER_RW( 0x7e800010 )
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#define CAM0_CLK_MASK 0xffffffff
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#define CAM0_CLK_WIDTH 32
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#define CAM0_CLK_RESET 0000000000
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#define CAM0_DAT0 HW_REGISTER_RW( 0x7e800014 )
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#define CAM0_DAT0_MASK 0xffffffff
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#define CAM0_DAT0_WIDTH 32
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#define CAM0_DAT0_RESET 0000000000
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#define CAM0_DAT1 HW_REGISTER_RW( 0x7e800018 )
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#define CAM0_DAT1_MASK 0xffffffff
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#define CAM0_DAT1_WIDTH 32
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#define CAM0_DAT1_RESET 0000000000
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#define CAM0_DAT2 HW_REGISTER_RW( 0x7e80001c )
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#define CAM0_DAT2_MASK 0xffffffff
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#define CAM0_DAT2_WIDTH 32
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#define CAM0_DAT2_RESET 0000000000
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#define CAM0_DAT3 HW_REGISTER_RW( 0x7e800020 )
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#define CAM0_DAT3_MASK 0xffffffff
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#define CAM0_DAT3_WIDTH 32
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#define CAM0_DAT3_RESET 0000000000
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#define CAM0_CMP0 HW_REGISTER_RW( 0x7e800024 )
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#define CAM0_CMP0_MASK 0xffffffff
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#define CAM0_CMP0_WIDTH 32
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#define CAM0_CMP0_RESET 0000000000
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#define CAM0_CMP1 HW_REGISTER_RW( 0x7e800028 )
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#define CAM0_CMP1_MASK 0xffffffff
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#define CAM0_CMP1_WIDTH 32
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#define CAM0_CMP1_RESET 0000000000
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#define CAM0_CAP0 HW_REGISTER_RW( 0x7e80002c )
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#define CAM0_CAP0_MASK 0xffffffff
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#define CAM0_CAP0_WIDTH 32
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#define CAM0_CAP0_RESET 0000000000
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#define CAM0_CAP1 HW_REGISTER_RW( 0x7e800030 )
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#define CAM0_CAP1_MASK 0xffffffff
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#define CAM0_CAP1_WIDTH 32
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#define CAM0_CAP1_RESET 0000000000
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#define CAM0_DBG0 HW_REGISTER_RW( 0x7e8000f0 )
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#define CAM0_DBG0_MASK 0xffffffff
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#define CAM0_DBG0_WIDTH 32
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#define CAM0_DBG0_RESET 0000000000
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#define CAM0_DBG1 HW_REGISTER_RW( 0x7e8000f4 )
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#define CAM0_DBG1_MASK 0xffffffff
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#define CAM0_DBG1_WIDTH 32
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#define CAM0_DBG1_RESET 0000000000
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#define CAM0_DBG2 HW_REGISTER_RW( 0x7e8000f8 )
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#define CAM0_DBG2_MASK 0xffffffff
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#define CAM0_DBG2_WIDTH 32
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#define CAM0_DBG2_RESET 0000000000
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#define CAM0_ICTL HW_REGISTER_RW( 0x7e800100 )
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#define CAM0_ICTL_MASK 0xffffffff
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#define CAM0_ICTL_WIDTH 32
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#define CAM0_ICTL_RESET 0000000000
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#define CAM0_ISTA HW_REGISTER_RW( 0x7e800104 )
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#define CAM0_ISTA_MASK 0xffffffff
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#define CAM0_ISTA_WIDTH 32
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#define CAM0_ISTA_RESET 0000000000
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#define CAM0_IDI HW_REGISTER_RW( 0x7e800108 )
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#define CAM0_IDI_MASK 0xffffffff
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#define CAM0_IDI_WIDTH 32
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#define CAM0_IDI_RESET 0000000000
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#define CAM0_IPIPE HW_REGISTER_RW( 0x7e80010c )
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#define CAM0_IPIPE_MASK 0xffffffff
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#define CAM0_IPIPE_WIDTH 32
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#define CAM0_IPIPE_RESET 0000000000
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#define CAM0_IBSA HW_REGISTER_RW( 0x7e800110 )
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#define CAM0_IBSA_MASK 0xffffffff
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#define CAM0_IBSA_WIDTH 32
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#define CAM0_IBSA_RESET 0000000000
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#define CAM0_IBEA HW_REGISTER_RW( 0x7e800114 )
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#define CAM0_IBEA_MASK 0xffffffff
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#define CAM0_IBEA_WIDTH 32
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#define CAM0_IBEA_RESET 0000000000
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#define CAM0_IBLS HW_REGISTER_RW( 0x7e800118 )
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#define CAM0_IBLS_MASK 0xffffffff
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#define CAM0_IBLS_WIDTH 32
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#define CAM0_IBLS_RESET 0000000000
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#define CAM0_IBWP HW_REGISTER_RW( 0x7e80011c )
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#define CAM0_IBWP_MASK 0xffffffff
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#define CAM0_IBWP_WIDTH 32
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#define CAM0_IBWP_RESET 0000000000
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#define CAM0_IHWIN HW_REGISTER_RW( 0x7e800120 )
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#define CAM0_IHWIN_MASK 0xffffffff
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#define CAM0_IHWIN_WIDTH 32
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#define CAM0_IHWIN_RESET 0000000000
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#define CAM0_IHSTA HW_REGISTER_RW( 0x7e800124 )
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#define CAM0_IHSTA_MASK 0xffffffff
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#define CAM0_IHSTA_WIDTH 32
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#define CAM0_IHSTA_RESET 0000000000
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#define CAM0_IVWIN HW_REGISTER_RW( 0x7e800128 )
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#define CAM0_IVWIN_MASK 0xffffffff
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#define CAM0_IVWIN_WIDTH 32
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#define CAM0_IVWIN_RESET 0000000000
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#define CAM0_IVSTA HW_REGISTER_RW( 0x7e80012c )
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#define CAM0_IVSTA_MASK 0xffffffff
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#define CAM0_IVSTA_WIDTH 32
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#define CAM0_IVSTA_RESET 0000000000
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#define CAM0_DCS HW_REGISTER_RW( 0x7e800200 )
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#define CAM0_DCS_MASK 0xffffffff
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#define CAM0_DCS_WIDTH 32
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#define CAM0_DCS_RESET 0000000000
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#define CAM0_DBSA HW_REGISTER_RW( 0x7e800204 )
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#define CAM0_DBSA_MASK 0xffffffff
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#define CAM0_DBSA_WIDTH 32
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#define CAM0_DBSA_RESET 0000000000
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#define CAM0_DBEA HW_REGISTER_RW( 0x7e800208 )
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#define CAM0_DBEA_MASK 0xffffffff
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#define CAM0_DBEA_WIDTH 32
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#define CAM0_DBEA_RESET 0000000000
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#define CAM0_DBWP HW_REGISTER_RW( 0x7e800208 )
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#define CAM0_DBWP_MASK 0xffffffff
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#define CAM0_DBWP_WIDTH 32
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#define CAM0_DBWP_RESET 0000000000
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