125 lines
9.5 KiB
C
Executable File
125 lines
9.5 KiB
C
Executable File
// This file was generated by the create_regs script
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#define DSI1_BASE 0x7e700000
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#define DSI1_APB_ID 0x64736934
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#define DSI1_CTRL HW_REGISTER_RW( 0x7e700000 )
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#define DSI1_CTRL_MASK 0xffffffff
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#define DSI1_CTRL_WIDTH 32
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#define DSI1_CTRL_RESET 0000000000
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#define DSI1_TXPKT1_C HW_REGISTER_RW( 0x7e700004 )
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#define DSI1_TXPKT1_C_MASK 0xffffffff
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#define DSI1_TXPKT1_C_WIDTH 32
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#define DSI1_TXPKT1_C_RESET 0000000000
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#define DSI1_TXPKT1_H HW_REGISTER_RW( 0x7e700008 )
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#define DSI1_TXPKT1_H_MASK 0xffffffff
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#define DSI1_TXPKT1_H_WIDTH 32
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#define DSI1_TXPKT1_H_RESET 0000000000
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#define DSI1_TXPKT2_C HW_REGISTER_RW( 0x7e70000c )
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#define DSI1_TXPKT2_C_MASK 0xffffffff
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#define DSI1_TXPKT2_C_WIDTH 32
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#define DSI1_TXPKT2_C_RESET 0000000000
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#define DSI1_TXPKT2_H HW_REGISTER_RW( 0x7e700010 )
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#define DSI1_TXPKT2_H_MASK 0xffffffff
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#define DSI1_TXPKT2_H_WIDTH 32
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#define DSI1_TXPKT2_H_RESET 0000000000
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#define DSI1_RXPKT1_H HW_REGISTER_RO( 0x7e700014 )
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#define DSI1_RXPKT1_H_MASK 0xffffffff
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#define DSI1_RXPKT1_H_WIDTH 32
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#define DSI1_RXPKT2_H HW_REGISTER_RO( 0x7e700018 )
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#define DSI1_RXPKT2_H_MASK 0xffffffff
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#define DSI1_RXPKT2_H_WIDTH 32
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#define DSI1_TXPKT_CMD_FIFO HW_REGISTER_RW( 0x7e70001c )
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#define DSI1_TXPKT_CMD_FIFO_MASK 0x000000ff
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#define DSI1_TXPKT_CMD_FIFO_WIDTH 8
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#define DSI1_TXPKT_PIXD_FIFO HW_REGISTER_RW( 0x7e700020 )
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#define DSI1_TXPKT_PIXD_FIFO_MASK 0xffffffff
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#define DSI1_TXPKT_PIXD_FIFO_WIDTH 32
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#define DSI1_TXPKT_PIXD_FIFO_RESET 0000000000
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#define DSI1_RXPKT_FIFO HW_REGISTER_RW( 0x7e700024 )
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#define DSI1_RXPKT_FIFO_MASK 0xffffffff
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#define DSI1_RXPKT_FIFO_WIDTH 32
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#define DSI1_RXPKT_FIFO_RESET 0000000000
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#define DSI1_DISP0_CTRL HW_REGISTER_RW( 0x7e700028 )
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#define DSI1_DISP0_CTRL_MASK 0xffffffff
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#define DSI1_DISP0_CTRL_WIDTH 32
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#define DSI1_DISP1_CTRL HW_REGISTER_RW( 0x7e70002c )
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#define DSI1_DISP1_CTRL_MASK 0xffffffff
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#define DSI1_DISP1_CTRL_WIDTH 32
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#define DSI1_INT_STAT HW_REGISTER_RW( 0x7e700030 )
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#define DSI1_INT_STAT_MASK 0xffffffff
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#define DSI1_INT_STAT_WIDTH 32
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#define DSI1_INT_EN HW_REGISTER_RW( 0x7e700034 )
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#define DSI1_INT_EN_MASK 0x0fffffff
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#define DSI1_INT_EN_WIDTH 28
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#define DSI1_INT_EN_RESET 0000000000
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#define DSI1_STAT HW_REGISTER_RW( 0x7e700038 )
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#define DSI1_STAT_MASK 0xffffffff
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#define DSI1_STAT_WIDTH 32
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#define DSI1_HSTX_TO_CNT HW_REGISTER_RW( 0x7e70003c )
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#define DSI1_HSTX_TO_CNT_MASK 0x00ffffff
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#define DSI1_HSTX_TO_CNT_WIDTH 24
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#define DSI1_HSTX_TO_CNT_RESET 0000000000
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#define DSI1_LPRX_TO_CNT HW_REGISTER_RW( 0x7e700040 )
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#define DSI1_LPRX_TO_CNT_MASK 0xffffffff
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#define DSI1_LPRX_TO_CNT_WIDTH 32
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#define DSI1_LPRX_TO_CNT_RESET 0000000000
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#define DSI1_TA_TO_CNT HW_REGISTER_RW( 0x7e700044 )
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#define DSI1_TA_TO_CNT_MASK 0xffffffff
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#define DSI1_TA_TO_CNT_WIDTH 32
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#define DSI1_TA_TO_CNT_RESET 0000000000
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#define DSI1_PR_TO_CNT HW_REGISTER_RW( 0x7e700048 )
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#define DSI1_PR_TO_CNT_MASK 0xffffffff
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#define DSI1_PR_TO_CNT_WIDTH 32
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#define DSI1_PR_TO_CNT_RESET 0000000000
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#define DSI1_PHYC HW_REGISTER_RW( 0x7e70004c )
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#define DSI1_PHYC_MASK 0xffffffff
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#define DSI1_PHYC_WIDTH 32
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#define DSI1_PHYC_RESET 0000000000
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#define DSI1_HS_CLT0 HW_REGISTER_RW( 0x7e700050 )
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#define DSI1_HS_CLT0_MASK 0xffffffff
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#define DSI1_HS_CLT0_WIDTH 32
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#define DSI1_HS_CLT0_RESET 0000000000
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#define DSI1_HS_CLT1 HW_REGISTER_RW( 0x7e700054 )
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#define DSI1_HS_CLT1_MASK 0xffffffff
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#define DSI1_HS_CLT1_WIDTH 32
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#define DSI1_HS_CLT1_RESET 0000000000
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#define DSI1_HS_CLT2 HW_REGISTER_RW( 0x7e700058 )
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#define DSI1_HS_CLT2_MASK 0xffffffff
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#define DSI1_HS_CLT2_WIDTH 32
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#define DSI1_HS_CLT2_RESET 0000000000
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#define DSI1_HS_DLT3 HW_REGISTER_RW( 0x7e70005c )
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#define DSI1_HS_DLT3_MASK 0xffffffff
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#define DSI1_HS_DLT3_WIDTH 32
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#define DSI1_HS_DLT3_RESET 0000000000
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#define DSI1_HS_DLT4 HW_REGISTER_RW( 0x7e700060 )
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#define DSI1_HS_DLT4_MASK 0xffffffff
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#define DSI1_HS_DLT4_WIDTH 32
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#define DSI1_HS_DLT4_RESET 0000000000
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#define DSI1_HS_DLT5 HW_REGISTER_RW( 0x7e700064 )
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#define DSI1_HS_DLT5_MASK 0xffffffff
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#define DSI1_HS_DLT5_WIDTH 32
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#define DSI1_HS_DLT5_RESET 0000000000
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#define DSI1_LP_DLT6 HW_REGISTER_RW( 0x7e700068 )
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#define DSI1_LP_DLT6_MASK 0xffffffff
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#define DSI1_LP_DLT6_WIDTH 32
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#define DSI1_LP_DLT6_RESET 0000000000
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#define DSI1_LP_DLT7 HW_REGISTER_RW( 0x7e70006c )
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#define DSI1_LP_DLT7_MASK 0xffffffff
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#define DSI1_LP_DLT7_WIDTH 32
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#define DSI1_LP_DLT7_RESET 0000000000
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#define DSI1_PHY_AFEC0 HW_REGISTER_RW( 0x7e700070 )
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#define DSI1_PHY_AFEC0_MASK 0xffffffff
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#define DSI1_PHY_AFEC0_WIDTH 32
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#define DSI1_PHY_AFEC0_RESET 0000000000
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#define DSI1_PHY_AFEC1 HW_REGISTER_RW( 0x7e700074 )
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#define DSI1_PHY_AFEC1_MASK 0xffffffff
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#define DSI1_PHY_AFEC1_WIDTH 32
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#define DSI1_PHY_AFEC1_RESET 0000000000
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#define DSI1_TST_SEL HW_REGISTER_RW( 0x7e700078 )
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#define DSI1_TST_SEL_MASK 0xffffffff
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#define DSI1_TST_SEL_WIDTH 32
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#define DSI1_TST_SEL_RESET 0000000000
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#define DSI1_TST_MON HW_REGISTER_RW( 0x7e70007c )
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#define DSI1_TST_MON_MASK 0xffffffff
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#define DSI1_TST_MON_WIDTH 32
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#define DSI1_TST_MON_RESET 0000000000
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