45 lines
3.4 KiB
C
Executable File
45 lines
3.4 KiB
C
Executable File
// This file was generated by the create_regs script
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#define FPGA_MB_BASE 0x7e20b700
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#define FPGA_MB_XSYS_BUILD_NUM HW_REGISTER_RO( 0x7e20b700 )
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#define FPGA_MB_XSYS_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XSYS_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XC0_BUILD_NUM HW_REGISTER_RO( 0x7e20b704 )
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#define FPGA_MB_XC0_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XC0_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b708 )
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#define FPGA_MB_XC1_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XC1_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XPERI_BUILD_NUM HW_REGISTER_RO( 0x7e20b70c )
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#define FPGA_MB_XPERI_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XPERI_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XH264_BUILD_NUM HW_REGISTER_RO( 0x7e20b710 )
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#define FPGA_MB_XH264_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XH264_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XV3D_BUILD_NUM HW_REGISTER_RO( 0x7e20b714 )
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#define FPGA_MB_XV3D_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XV3D_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XSLC1_BUILD_NUM HW_REGISTER_RO( 0x7e20b718 )
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#define FPGA_MB_XSLC1_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XSLC1_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XSLC2_BUILD_NUM HW_REGISTER_RO( 0x7e20b71c )
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#define FPGA_MB_XSLC2_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XSLC2_BUILD_NUM_WIDTH 32
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#define FPGA_MB_XSLC3_BUILD_NUM HW_REGISTER_RO( 0x7e20b720 )
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#define FPGA_MB_XSLC3_BUILD_NUM_MASK 0xffffffff
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#define FPGA_MB_XSLC3_BUILD_NUM_WIDTH 32
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#define FPGA_MB_CORE_CLK_FREQ HW_REGISTER_RO( 0x7e20b724 )
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#define FPGA_MB_CORE_CLK_FREQ_MASK 0xffffffff
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#define FPGA_MB_CORE_CLK_FREQ_WIDTH 32
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#define FPGA_MB_SDC_CLK_FREQ HW_REGISTER_RO( 0x7e20b728 )
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#define FPGA_MB_SDC_CLK_FREQ_MASK 0xffffffff
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#define FPGA_MB_SDC_CLK_FREQ_WIDTH 32
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#define FPGA_MB_SDC_H264_FREQ HW_REGISTER_RO( 0x7e20b72c )
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#define FPGA_MB_SDC_H264_FREQ_MASK 0xffffffff
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#define FPGA_MB_SDC_H264_FREQ_WIDTH 32
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#define FPGA_MB_SDC_V3D_FREQ HW_REGISTER_RO( 0x7e20b730 )
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#define FPGA_MB_SDC_V3D_FREQ_MASK 0xffffffff
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#define FPGA_MB_SDC_V3D_FREQ_WIDTH 32
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#define FPGA_MB_SDC_ISP_FREQ HW_REGISTER_RO( 0x7e20b734 )
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#define FPGA_MB_SDC_ISP_FREQ_MASK 0xffffffff
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#define FPGA_MB_SDC_ISP_FREQ_WIDTH 32
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