207 lines
14 KiB
C
Executable File
207 lines
14 KiB
C
Executable File
#define FPGA_A0_BASE 0x7e213000
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#define FPGA_B0_BASE 0x7e214000
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#define FPGA_CTRL0_OFFSET 0x08
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#define FPGA_STATUS0_OFFSET 0x0C
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// This file was generated by the create_regs script
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#define FPGA_BASE 0x7e20b600
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#define FPGA_APB_ID 0x66706761
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#define FPGA_VERSION HW_REGISTER_RO( 0x7e20b600 )
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#define FPGA_VERSION_MASK 0xffffffff
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#define FPGA_VERSION_WIDTH 32
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#define FPGA_SCRATCH HW_REGISTER_RW( 0x7e20b604 )
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#define FPGA_SCRATCH_MASK 0xffffffff
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#define FPGA_SCRATCH_WIDTH 32
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#define FPGA_CTRL0 HW_REGISTER_RW( 0x7e20b608 )
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#define FPGA_CTRL0_MASK 0xfffff3fff
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#define FPGA_CTRL0_WIDTH 36
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#define FPGA_CTRL0_SPARE_OUT_BITS 31:20
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#define FPGA_CTRL0_SPARE_OUT_SET 0xfff00000
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#define FPGA_CTRL0_SPARE_OUT_CLR 0x000fffff
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#define FPGA_CTRL0_SPARE_OUT_MSB 31
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#define FPGA_CTRL0_SPARE_OUT_LSB 20
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#define FPGA_CTRL0_LV_SPARE_OUT_BITS 19:18
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#define FPGA_CTRL0_LV_SPARE_OUT_SET 0x000c0000
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#define FPGA_CTRL0_LV_SPARE_OUT_CLR 0xfff3ffff
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#define FPGA_CTRL0_LV_SPARE_OUT_MSB 19
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#define FPGA_CTRL0_LV_SPARE_OUT_LSB 18
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#define FPGA_CTRL0_TERMEN_CLK_BITS 17:17
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#define FPGA_CTRL0_TERMEN_CLK_SET 0x00020000
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#define FPGA_CTRL0_TERMEN_CLK_CLR 0xfffdffff
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#define FPGA_CTRL0_TERMEN_CLK_MSB 17
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#define FPGA_CTRL0_TERMEN_CLK_LSB 17
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#define FPGA_CTRL0_TERMEN_DO_BITS 16:16
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#define FPGA_CTRL0_TERMEN_DO_SET 0x00010000
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#define FPGA_CTRL0_TERMEN_DO_CLR 0xfffeffff
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#define FPGA_CTRL0_TERMEN_DO_MSB 16
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#define FPGA_CTRL0_TERMEN_DO_LSB 16
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#define FPGA_CTRL0_TV_ACTIVITY_BITS 13:13
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#define FPGA_CTRL0_TV_ACTIVITY_SET 0x00002000
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#define FPGA_CTRL0_TV_ACTIVITY_CLR 0xffffdfff
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#define FPGA_CTRL0_TV_ACTIVITY_MSB 13
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#define FPGA_CTRL0_TV_ACTIVITY_LSB 13
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#define FPGA_CTRL0_SPI0_SEL_B_BITS 12:12
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#define FPGA_CTRL0_SPI0_SEL_B_SET 0x00001000
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#define FPGA_CTRL0_SPI0_SEL_B_CLR 0xffffefff
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#define FPGA_CTRL0_SPI0_SEL_B_MSB 12
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#define FPGA_CTRL0_SPI0_SEL_B_LSB 12
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#define FPGA_CTRL0_DISP_BUFFER_BITS 11:11
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#define FPGA_CTRL0_DISP_BUFFER_SET 0x00000800
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#define FPGA_CTRL0_DISP_BUFFER_CLR 0xfffff7ff
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#define FPGA_CTRL0_DISP_BUFFER_MSB 11
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#define FPGA_CTRL0_DISP_BUFFER_LSB 11
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#define FPGA_CTRL0_SPI1_SEL_BITS 10:10
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#define FPGA_CTRL0_SPI1_SEL_SET 0x00000400
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#define FPGA_CTRL0_SPI1_SEL_CLR 0xfffffbff
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#define FPGA_CTRL0_SPI1_SEL_MSB 10
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#define FPGA_CTRL0_SPI1_SEL_LSB 10
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#define FPGA_CTRL0_SPI0_SEL_A_BITS 9:9
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#define FPGA_CTRL0_SPI0_SEL_A_SET 0x00000200
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#define FPGA_CTRL0_SPI0_SEL_A_CLR 0xfffffdff
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#define FPGA_CTRL0_SPI0_SEL_A_MSB 9
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#define FPGA_CTRL0_SPI0_SEL_A_LSB 9
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#define FPGA_CTRL0_SW_SPI_CS_BITS 8:8
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#define FPGA_CTRL0_SW_SPI_CS_SET 0x00000100
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#define FPGA_CTRL0_SW_SPI_CS_CLR 0xfffffeff
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#define FPGA_CTRL0_SW_SPI_CS_MSB 8
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#define FPGA_CTRL0_SW_SPI_CS_LSB 8
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#define FPGA_CTRL0_SW_SPI_SDA_O_BITS 7:7
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#define FPGA_CTRL0_SW_SPI_SDA_O_SET 0x00000080
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#define FPGA_CTRL0_SW_SPI_SDA_O_CLR 0xffffff7f
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#define FPGA_CTRL0_SW_SPI_SDA_O_MSB 7
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#define FPGA_CTRL0_SW_SPI_SDA_O_LSB 7
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#define FPGA_CTRL0_SW_SPI_SCL_BITS 6:6
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#define FPGA_CTRL0_SW_SPI_SCL_SET 0x00000040
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#define FPGA_CTRL0_SW_SPI_SCL_CLR 0xffffffbf
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#define FPGA_CTRL0_SW_SPI_SCL_MSB 6
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#define FPGA_CTRL0_SW_SPI_SCL_LSB 6
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#define FPGA_CTRL0_DIS_SW_SPI_BITS 5:5
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#define FPGA_CTRL0_DIS_SW_SPI_SET 0x00000020
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#define FPGA_CTRL0_DIS_SW_SPI_CLR 0xffffffdf
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#define FPGA_CTRL0_DIS_SW_SPI_MSB 5
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#define FPGA_CTRL0_DIS_SW_SPI_LSB 5
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#define FPGA_CTRL0_SD_PSU_EN_BITS 4:4
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#define FPGA_CTRL0_SD_PSU_EN_SET 0x00000010
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#define FPGA_CTRL0_SD_PSU_EN_CLR 0xffffffef
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#define FPGA_CTRL0_SD_PSU_EN_MSB 4
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#define FPGA_CTRL0_SD_PSU_EN_LSB 4
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#define FPGA_CTRL0_DIS_RST_BITS 3:3
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#define FPGA_CTRL0_DIS_RST_SET 0x00000008
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#define FPGA_CTRL0_DIS_RST_CLR 0xfffffff7
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#define FPGA_CTRL0_DIS_RST_MSB 3
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#define FPGA_CTRL0_DIS_RST_LSB 3
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#define FPGA_CTRL0_DIS_CTL2_BITS 2:2
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#define FPGA_CTRL0_DIS_CTL2_SET 0x00000004
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#define FPGA_CTRL0_DIS_CTL2_CLR 0xfffffffb
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#define FPGA_CTRL0_DIS_CTL2_MSB 2
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#define FPGA_CTRL0_DIS_CTL2_LSB 2
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#define FPGA_CTRL0_DIS_BL_BITS 1:1
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#define FPGA_CTRL0_DIS_BL_SET 0x00000002
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#define FPGA_CTRL0_DIS_BL_CLR 0xfffffffd
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#define FPGA_CTRL0_DIS_BL_MSB 1
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#define FPGA_CTRL0_DIS_BL_LSB 1
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#define FPGA_CTRL0_DIS_CTL0_BITS 0:0
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#define FPGA_CTRL0_DIS_CTL0_SET 0x00000001
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#define FPGA_CTRL0_DIS_CTL0_CLR 0xfffffffe
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#define FPGA_CTRL0_DIS_CTL0_MSB 0
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#define FPGA_CTRL0_DIS_CTL0_LSB 0
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#define FPGA_CTRL0_CAM_CTL2_BITS 2:2
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#define FPGA_CTRL0_CAM_CTL2_SET 0x00000004
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#define FPGA_CTRL0_CAM_CTL2_CLR 0xfffffffb
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#define FPGA_CTRL0_CAM_CTL2_MSB 2
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#define FPGA_CTRL0_CAM_CTL2_LSB 2
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#define FPGA_CTRL0_CAM_CTL1_BITS 1:1
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#define FPGA_CTRL0_CAM_CTL1_SET 0x00000002
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#define FPGA_CTRL0_CAM_CTL1_CLR 0xfffffffd
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#define FPGA_CTRL0_CAM_CTL1_MSB 1
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#define FPGA_CTRL0_CAM_CTL1_LSB 1
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#define FPGA_CTRL0_CAM_CTL0_BITS 0:0
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#define FPGA_CTRL0_CAM_CTL0_SET 0x00000001
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#define FPGA_CTRL0_CAM_CTL0_CLR 0xfffffffe
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#define FPGA_CTRL0_CAM_CTL0_MSB 0
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#define FPGA_CTRL0_CAM_CTL0_LSB 0
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#define FPGA_STATUS0 HW_REGISTER_RO( 0x7e20b60c )
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#define FPGA_STATUS0_MASK 0xfff800ff
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#define FPGA_STATUS0_WIDTH 32
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#define FPGA_STATUS0_SPARE_IN_BITS 31:19
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#define FPGA_STATUS0_SPARE_IN_SET 0xfff80000
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#define FPGA_STATUS0_SPARE_IN_CLR 0x0007ffff
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#define FPGA_STATUS0_SPARE_IN_MSB 31
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#define FPGA_STATUS0_SPARE_IN_LSB 19
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#define FPGA_STATUS0_SW_SPI_SPI_IN_BITS 7:7
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#define FPGA_STATUS0_SW_SPI_SPI_IN_SET 0x00000080
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#define FPGA_STATUS0_SW_SPI_SPI_IN_CLR 0xffffff7f
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#define FPGA_STATUS0_SW_SPI_SPI_IN_MSB 7
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#define FPGA_STATUS0_SW_SPI_SPI_IN_LSB 7
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#define FPGA_STATUS0_NAND_RNB_BITS 6:6
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#define FPGA_STATUS0_NAND_RNB_SET 0x00000040
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#define FPGA_STATUS0_NAND_RNB_CLR 0xffffffbf
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#define FPGA_STATUS0_NAND_RNB_MSB 6
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#define FPGA_STATUS0_NAND_RNB_LSB 6
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#define FPGA_STATUS0_SD_CD_BITS 5:5
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#define FPGA_STATUS0_SD_CD_SET 0x00000020
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#define FPGA_STATUS0_SD_CD_CLR 0xffffffdf
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#define FPGA_STATUS0_SD_CD_MSB 5
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#define FPGA_STATUS0_SD_CD_LSB 5
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#define FPGA_STATUS0_SD_WP_BITS 4:4
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#define FPGA_STATUS0_SD_WP_SET 0x00000010
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#define FPGA_STATUS0_SD_WP_CLR 0xffffffef
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#define FPGA_STATUS0_SD_WP_MSB 4
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#define FPGA_STATUS0_SD_WP_LSB 4
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#define FPGA_STATUS0_HW_ID_BITS 3:0
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#define FPGA_STATUS0_HW_ID_SET 0x0000000f
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#define FPGA_STATUS0_HW_ID_CLR 0xfffffff0
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#define FPGA_STATUS0_HW_ID_MSB 3
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#define FPGA_STATUS0_HW_ID_LSB 0
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#define FPGA_DCM_WR_DATA HW_REGISTER_RW( 0x7e20b610 )
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#define FPGA_DCM_WR_DATA_MASK 0x00ffffff
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#define FPGA_DCM_WR_DATA_WIDTH 24
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#define FPGA_DCM_WR_DATA_ADDRESS_BITS 23:16
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#define FPGA_DCM_WR_DATA_ADDRESS_SET 0x00ff0000
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#define FPGA_DCM_WR_DATA_ADDRESS_CLR 0xff00ffff
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#define FPGA_DCM_WR_DATA_ADDRESS_MSB 23
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#define FPGA_DCM_WR_DATA_ADDRESS_LSB 16
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#define FPGA_DCM_WR_DATA_DATA_BITS 15:0
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#define FPGA_DCM_WR_DATA_DATA_SET 0x0000ffff
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#define FPGA_DCM_WR_DATA_DATA_CLR 0xffff0000
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#define FPGA_DCM_WR_DATA_DATA_MSB 15
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#define FPGA_DCM_WR_DATA_DATA_LSB 0
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#define FPGA_DCM_CTRL HW_REGISTER_RW( 0x7e20b614 )
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#define FPGA_DCM_CTRL_MASK 0xff0fffff
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#define FPGA_DCM_CTRL_WIDTH 32
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#define FPGA_DCM_CTRL_PERI_WR_EN_BITS 31:28
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#define FPGA_DCM_CTRL_PERI_WR_EN_SET 0xf0000000
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#define FPGA_DCM_CTRL_PERI_WR_EN_CLR 0x0fffffff
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#define FPGA_DCM_CTRL_PERI_WR_EN_MSB 31
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#define FPGA_DCM_CTRL_PERI_WR_EN_LSB 28
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#define FPGA_DCM_CTRL_PERI_EN_BITS 27:24
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#define FPGA_DCM_CTRL_PERI_EN_SET 0x0f000000
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#define FPGA_DCM_CTRL_PERI_EN_CLR 0xf0ffffff
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#define FPGA_DCM_CTRL_PERI_EN_MSB 27
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#define FPGA_DCM_CTRL_PERI_EN_LSB 24
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#define FPGA_DCM_CTRL_PERI_RST_BITS 19:16
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#define FPGA_DCM_CTRL_PERI_RST_SET 0x000f0000
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#define FPGA_DCM_CTRL_PERI_RST_CLR 0xfff0ffff
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#define FPGA_DCM_CTRL_PERI_RST_MSB 19
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#define FPGA_DCM_CTRL_PERI_RST_LSB 16
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#define FPGA_DCM_CTRL_REMOTE_EN_BITS 12:8
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#define FPGA_DCM_CTRL_REMOTE_EN_SET 0x00001f00
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#define FPGA_DCM_CTRL_REMOTE_EN_CLR 0xffffe0ff
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#define FPGA_DCM_CTRL_REMOTE_EN_MSB 12
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#define FPGA_DCM_CTRL_REMOTE_EN_LSB 8
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#define FPGA_DCM_CTRL_REMOTE_RST_BITS 4:0
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#define FPGA_DCM_CTRL_REMOTE_RST_SET 0x0000001f
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#define FPGA_DCM_CTRL_REMOTE_RST_CLR 0xffffffe0
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#define FPGA_DCM_CTRL_REMOTE_RST_MSB 4
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#define FPGA_DCM_CTRL_REMOTE_RST_LSB 0
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#define FPGA_DCM_RD_DATA HW_REGISTER_RO( 0x7e20b618 )
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#define FPGA_DCM_RD_DATA_MASK 0x0000ffff
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#define FPGA_DCM_RD_DATA_WIDTH 16
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#define FPGA_DCM_RD_DATA_DATA_BITS 15:0
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#define FPGA_DCM_RD_DATA_DATA_SET 0x0000ffff
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#define FPGA_DCM_RD_DATA_DATA_CLR 0xffff0000
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#define FPGA_DCM_RD_DATA_DATA_MSB 15
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#define FPGA_DCM_RD_DATA_DATA_LSB 0
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