89 lines
6.5 KiB
C
Executable File
89 lines
6.5 KiB
C
Executable File
// This file was generated by the create_regs script
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#define L2_BASE 0x7ee01000
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#define L2_APB_ID 0x4c324343
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#define L2_CONT_OFF HW_REGISTER_RW( 0x7ee01000 )
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#define L2_CONT_OFF_MASK 0x00ff0c3f
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#define L2_CONT_OFF_WIDTH 24
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#define L2_CONT_OFF_RESET 0000000000
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#define L2_CONT_OFF_l2_flush_core_limit_BITS 23:20
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#define L2_CONT_OFF_l2_flush_core_limit_SET 0x00f00000
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#define L2_CONT_OFF_l2_flush_core_limit_CLR 0xff0fffff
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#define L2_CONT_OFF_l2_flush_core_limit_MSB 23
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#define L2_CONT_OFF_l2_flush_core_limit_LSB 20
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#define L2_CONT_OFF_l2_flush_flush_limit_BITS 19:16
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#define L2_CONT_OFF_l2_flush_flush_limit_SET 0x000f0000
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#define L2_CONT_OFF_l2_flush_flush_limit_CLR 0xfff0ffff
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#define L2_CONT_OFF_l2_flush_flush_limit_MSB 19
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#define L2_CONT_OFF_l2_flush_flush_limit_LSB 16
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#define L2_CONT_OFF_l2_standby_BITS 11:10
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#define L2_CONT_OFF_l2_standby_SET 0x00000c00
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#define L2_CONT_OFF_l2_standby_CLR 0xfffff3ff
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#define L2_CONT_OFF_l2_standby_MSB 11
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#define L2_CONT_OFF_l2_standby_LSB 10
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#define L2_CONT_OFF_l2_enable_stats_BITS 5:5
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#define L2_CONT_OFF_l2_enable_stats_SET 0x00000020
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#define L2_CONT_OFF_l2_enable_stats_CLR 0xffffffdf
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#define L2_CONT_OFF_l2_enable_stats_MSB 5
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#define L2_CONT_OFF_l2_enable_stats_LSB 5
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#define L2_CONT_OFF_l2_flush_mode_BITS 4:3
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#define L2_CONT_OFF_l2_flush_mode_SET 0x00000018
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#define L2_CONT_OFF_l2_flush_mode_CLR 0xffffffe7
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#define L2_CONT_OFF_l2_flush_mode_MSB 4
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#define L2_CONT_OFF_l2_flush_mode_LSB 3
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#define L2_CONT_OFF_l2_flush_BITS 2:2
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#define L2_CONT_OFF_l2_flush_SET 0x00000004
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#define L2_CONT_OFF_l2_flush_CLR 0xfffffffb
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#define L2_CONT_OFF_l2_flush_MSB 2
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#define L2_CONT_OFF_l2_flush_LSB 2
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#define L2_CONT_OFF_l2_no_wr_allocate_BITS 1:1
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#define L2_CONT_OFF_l2_no_wr_allocate_SET 0x00000002
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#define L2_CONT_OFF_l2_no_wr_allocate_CLR 0xfffffffd
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#define L2_CONT_OFF_l2_no_wr_allocate_MSB 1
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#define L2_CONT_OFF_l2_no_wr_allocate_LSB 1
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#define L2_CONT_OFF_l2_disable_BITS 0:0
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#define L2_CONT_OFF_l2_disable_SET 0x00000001
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#define L2_CONT_OFF_l2_disable_CLR 0xfffffffe
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#define L2_CONT_OFF_l2_disable_MSB 0
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#define L2_CONT_OFF_l2_disable_LSB 0
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#define L2_FLUSH_STA HW_REGISTER_RW( 0x7ee01004 )
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#define L2_FLUSH_STA_MASK 0x0fffffe0
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#define L2_FLUSH_STA_WIDTH 28
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#define L2_FLUSH_STA_RESET 0000000000
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#define L2_FLUSH_END HW_REGISTER_RW( 0x7ee01008 )
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#define L2_FLUSH_END_MASK 0x0fffffe0
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#define L2_FLUSH_END_WIDTH 28
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#define L2_FLUSH_END_RESET 0x0fffffe0
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#define L2_L2_ALIAS_EXCEPTION HW_REGISTER_RW( 0x7ee01080 )
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#define L2_L2_ALIAS_EXCEPTION_RESET 0000000000
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#define L2_L2_ALIAS_EXCEPTION_ID HW_REGISTER_RO( 0x7ee01084 )
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#define L2_L2_ALIAS_EXCEPTION_ID_RESET 0000000000
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#define L2_L2_ALIAS_EXCEPTION_ADDR HW_REGISTER_RO( 0x7ee01088 )
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#define L2_L2_ALIAS_EXCEPTION_ADDR_RESET 0000000000
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#define L2_RD_HITS HW_REGISTER_RW( 0x7ee01100 )
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#define L2_RD_HITS_MASK 0xffffffff
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#define L2_RD_HITS_WIDTH 32
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#define L2_RD_MISSES HW_REGISTER_RO( 0x7ee01104 )
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#define L2_RD_MISSES_MASK 0xffffffff
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#define L2_RD_MISSES_WIDTH 32
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#define L2_WR_HITS HW_REGISTER_RO( 0x7ee01108 )
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#define L2_WR_HITS_MASK 0xffffffff
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#define L2_WR_HITS_WIDTH 32
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#define L2_WR_MISSES HW_REGISTER_RO( 0x7ee0110c )
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#define L2_WR_MISSES_MASK 0xffffffff
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#define L2_WR_MISSES_WIDTH 32
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#define L2_WR_BACKS HW_REGISTER_RO( 0x7ee01110 )
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#define L2_WR_BACKS_MASK 0xffffffff
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#define L2_WR_BACKS_WIDTH 32
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#define L2_IN_FLIGHT HW_REGISTER_RO( 0x7ee01114 )
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#define L2_IN_FLIGHT_MASK 0x0000000f
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#define L2_IN_FLIGHT_WIDTH 4
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#define L2_STALLS HW_REGISTER_RO( 0x7ee0111c )
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#define L2_STALLS_MASK 0xffffffff
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#define L2_STALLS_WIDTH 32
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#define L2_TAG_STALLS HW_REGISTER_RO( 0x7ee01120 )
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#define L2_TAG_STALLS_MASK 0xffffffff
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#define L2_TAG_STALLS_WIDTH 32
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#define L2_SD_STALLS HW_REGISTER_RO( 0x7ee01124 )
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#define L2_SD_STALLS_MASK 0xffffffff
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#define L2_SD_STALLS_WIDTH 32
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