Wolfgang Spraul
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f2a2c5d2b7
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wires left and right
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2012-07-28 07:42:31 +02:00 |
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Wolfgang Spraul
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1dadb4c381
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started with global clock wiring
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2012-07-27 16:01:34 +02:00 |
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Wolfgang Spraul
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904108d50a
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finished tile positioning cleanup
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2012-07-27 09:10:09 +02:00 |
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Wolfgang Spraul
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3b9fa11659
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tile positioning cleanup p1
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2012-07-27 07:45:26 +02:00 |
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Wolfgang Spraul
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f7ada88c59
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some dcm and pll wiring
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2012-07-27 03:31:30 +02:00 |
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Wolfgang Spraul
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ae2438cca0
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cleanup, wires, new_fp prints static connections
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2012-07-26 05:26:27 +02:00 |
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Wolfgang Spraul
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9ecc9d7475
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first steps in logic wires
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2012-07-25 14:01:24 +02:00 |
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Wolfgang Spraul
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c5098634c4
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wires
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2012-07-25 10:03:25 +02:00 |
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Wolfgang Spraul
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f8d1911cd2
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wires 1.1%
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2012-07-25 04:58:40 +02:00 |
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Wolfgang Spraul
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c9718d0372
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wires
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2012-07-25 03:03:23 +02:00 |
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Wolfgang Spraul
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44cd3b0b7f
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wires
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2012-07-24 15:38:01 +02:00 |
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Wolfgang Spraul
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7f74817e78
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modeling wires, about 0.7% of them done
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2012-07-24 05:49:14 +02:00 |
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Wolfgang Spraul
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a17588fac5
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modeled first line - NN2
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2012-07-23 10:34:28 +02:00 |
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Wolfgang Spraul
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b4ad7801b0
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minor model cleanup
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2012-07-21 06:04:08 +02:00 |
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Wolfgang Spraul
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970eb4eee9
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added simple hashed string array for tile and wire names
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2012-07-19 17:29:25 +02:00 |
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Wolfgang Spraul
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d1e8d5f557
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moved model into separate file so multiple utils can use it
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2012-07-17 10:58:07 +02:00 |
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