179 lines
13 KiB
C
Executable File
179 lines
13 KiB
C
Executable File
// This file was generated by the create_regs script
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#define DSI0_BASE 0x7e209000
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#define DSI0_APB_ID 0x00647369
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#define DSI0_CTRL HW_REGISTER_RW( 0x7e209000 )
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#define DSI0_CTRL_MASK 0x00000007
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#define DSI0_CTRL_WIDTH 3
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#define DSI0_CTRL_RESET 0000000000
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#define DSI0_CTRL_CTRL2_BITS 2:2
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#define DSI0_CTRL_CTRL2_SET 0x00000004
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#define DSI0_CTRL_CTRL2_CLR 0xfffffffb
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#define DSI0_CTRL_CTRL2_MSB 2
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#define DSI0_CTRL_CTRL2_LSB 2
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#define DSI0_CTRL_CTRL1_BITS 1:1
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#define DSI0_CTRL_CTRL1_SET 0x00000002
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#define DSI0_CTRL_CTRL1_CLR 0xfffffffd
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#define DSI0_CTRL_CTRL1_MSB 1
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#define DSI0_CTRL_CTRL1_LSB 1
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#define DSI0_CTRL_CTRL0_BITS 0:0
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#define DSI0_CTRL_CTRL0_SET 0x00000001
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#define DSI0_CTRL_CTRL0_CLR 0xfffffffe
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#define DSI0_CTRL_CTRL0_MSB 0
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#define DSI0_CTRL_CTRL0_LSB 0
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#define DSI0_CMD_PKTC HW_REGISTER_RW( 0x7e209004 )
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#define DSI0_CMD_PKTC_MASK 0xffffffff
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#define DSI0_CMD_PKTC_WIDTH 32
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#define DSI0_CMD_PKTC_RESET 0000000000
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#define DSI0_CMD_PKTH HW_REGISTER_RW( 0x7e209008 )
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#define DSI0_CMD_PKTH_MASK 0xffffffff
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#define DSI0_CMD_PKTH_WIDTH 32
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#define DSI0_CMD_PKTH_RESET 0000000000
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#define DSI0_RX1_PKTH HW_REGISTER_RO( 0x7e20900c )
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#define DSI0_RX1_PKTH_MASK 0xffffffff
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#define DSI0_RX1_PKTH_WIDTH 32
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#define DSI0_RX2_PKTH HW_REGISTER_RO( 0x7e209010 )
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#define DSI0_RX2_PKTH_MASK 0xffffffff
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#define DSI0_RX2_PKTH_WIDTH 32
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#define DSI0_CMD_DATAF HW_REGISTER_RW( 0x7e209014 )
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#define DSI0_CMD_DATAF_MASK 0x000000ff
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#define DSI0_CMD_DATAF_WIDTH 8
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#define DSI0_DISP0_CTR HW_REGISTER_RW( 0x7e209018 )
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#define DSI0_DISP0_CTR_MASK 0xffffffff
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#define DSI0_DISP0_CTR_WIDTH 32
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#define DSI0_DISP0_CTR_RESET 0000000000
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#define DSI0_DISP1_CTR HW_REGISTER_RW( 0x7e20901c )
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#define DSI0_DISP1_CTR_MASK 0xffffffff
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#define DSI0_DISP1_CTR_WIDTH 32
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#define DSI0_DISP1_CTR_RESET 0000000000
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#define DSI0_PIX_FIFO HW_REGISTER_RW( 0x7e209020 )
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#define DSI0_PIX_FIFO_MASK 0xffffffff
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#define DSI0_PIX_FIFO_WIDTH 32
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#define DSI0_INT_STAT HW_REGISTER_RW( 0x7e209024 )
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#define DSI0_INT_STAT_MASK 0xffffffff
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#define DSI0_INT_STAT_WIDTH 32
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#define DSI0_INT_EN HW_REGISTER_RW( 0x7e209028 )
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#define DSI0_INT_EN_MASK 0x0fffffff
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#define DSI0_INT_EN_WIDTH 28
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#define DSI0_INT_EN_RESET 0000000000
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#define DSI0_STAT HW_REGISTER_RW( 0x7e20902c )
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#define DSI0_STAT_MASK 0xffffffff
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#define DSI0_STAT_WIDTH 32
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#define DSI0_HSTX_TO_C HW_REGISTER_RW( 0x7e209030 )
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#define DSI0_HSTX_TO_C_MASK 0x00ffffff
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#define DSI0_HSTX_TO_C_WIDTH 24
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#define DSI0_HSTX_TO_C_RESET 0000000000
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#define DSI0_LPRX_TO_C HW_REGISTER_RW( 0x7e209034 )
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#define DSI0_LPRX_TO_C_MASK 0xffffffff
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#define DSI0_LPRX_TO_C_WIDTH 32
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#define DSI0_LPRX_TO_C_RESET 0000000000
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#define DSI0_TA_TO_CNT HW_REGISTER_RW( 0x7e209038 )
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#define DSI0_TA_TO_CNT_MASK 0xffffffff
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#define DSI0_TA_TO_CNT_WIDTH 32
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#define DSI0_TA_TO_CNT_RESET 0000000000
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#define DSI0_PR_TO_CNT HW_REGISTER_RW( 0x7e20903c )
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#define DSI0_PR_TO_CNT_MASK 0xffffffff
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#define DSI0_PR_TO_CNT_WIDTH 32
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#define DSI0_PR_TO_CNT_RESET 0000000000
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#define DSI0_PHYC HW_REGISTER_RW( 0x7e209040 )
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#define DSI0_PHYC_MASK 0x0003f777
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#define DSI0_PHYC_WIDTH 18
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#define DSI0_PHYC_RESET 0000000000
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#define DSI0_PHYC_dsi_esc_lpdt_BITS 17:12
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#define DSI0_PHYC_dsi_esc_lpdt_SET 0x0003f000
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#define DSI0_PHYC_dsi_esc_lpdt_CLR 0xfffc0fff
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#define DSI0_PHYC_dsi_esc_lpdt_MSB 17
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#define DSI0_PHYC_dsi_esc_lpdt_LSB 12
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#define DSI0_PHYC_txhsclk_cont_sync_BITS 10:10
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#define DSI0_PHYC_txhsclk_cont_sync_SET 0x00000400
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#define DSI0_PHYC_txhsclk_cont_sync_CLR 0xfffffbff
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#define DSI0_PHYC_txhsclk_cont_sync_MSB 10
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#define DSI0_PHYC_txhsclk_cont_sync_LSB 10
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#define DSI0_PHYC_txulps_clk_sync_BITS 9:9
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#define DSI0_PHYC_txulps_clk_sync_SET 0x00000200
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#define DSI0_PHYC_txulps_clk_sync_CLR 0xfffffdff
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#define DSI0_PHYC_txulps_clk_sync_MSB 9
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#define DSI0_PHYC_txulps_clk_sync_LSB 9
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#define DSI0_PHYC_clane_hsen_sync_BITS 8:8
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#define DSI0_PHYC_clane_hsen_sync_SET 0x00000100
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#define DSI0_PHYC_clane_hsen_sync_CLR 0xfffffeff
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#define DSI0_PHYC_clane_hsen_sync_MSB 8
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#define DSI0_PHYC_clane_hsen_sync_LSB 8
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#define DSI0_PHYC_txulpshs_1_sync_BITS 6:6
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#define DSI0_PHYC_txulpshs_1_sync_SET 0x00000040
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#define DSI0_PHYC_txulpshs_1_sync_CLR 0xffffffbf
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#define DSI0_PHYC_txulpshs_1_sync_MSB 6
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#define DSI0_PHYC_txulpshs_1_sync_LSB 6
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#define DSI0_PHYC_dlane_hsen_1_sync_BITS 5:5
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#define DSI0_PHYC_dlane_hsen_1_sync_SET 0x00000020
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#define DSI0_PHYC_dlane_hsen_1_sync_CLR 0xffffffdf
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#define DSI0_PHYC_dlane_hsen_1_sync_MSB 5
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#define DSI0_PHYC_dlane_hsen_1_sync_LSB 5
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#define DSI0_PHYC_unused_BITS 4:4
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#define DSI0_PHYC_unused_SET 0x00000010
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#define DSI0_PHYC_unused_CLR 0xffffffef
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#define DSI0_PHYC_unused_MSB 4
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#define DSI0_PHYC_unused_LSB 4
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#define DSI0_PHYC_forcehsstop_sync_BITS 2:2
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#define DSI0_PHYC_forcehsstop_sync_SET 0x00000004
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#define DSI0_PHYC_forcehsstop_sync_CLR 0xfffffffb
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#define DSI0_PHYC_forcehsstop_sync_MSB 2
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#define DSI0_PHYC_forcehsstop_sync_LSB 2
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#define DSI0_PHYC_txulpshs_0_sync_BITS 1:1
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#define DSI0_PHYC_txulpshs_0_sync_SET 0x00000002
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#define DSI0_PHYC_txulpshs_0_sync_CLR 0xfffffffd
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#define DSI0_PHYC_txulpshs_0_sync_MSB 1
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#define DSI0_PHYC_txulpshs_0_sync_LSB 1
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#define DSI0_PHYC_dlane_hsen_0_sync_BITS 0:0
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#define DSI0_PHYC_dlane_hsen_0_sync_SET 0x00000001
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#define DSI0_PHYC_dlane_hsen_0_sync_CLR 0xfffffffe
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#define DSI0_PHYC_dlane_hsen_0_sync_MSB 0
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#define DSI0_PHYC_dlane_hsen_0_sync_LSB 0
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#define DSI0_HS_CLT0 HW_REGISTER_RW( 0x7e209044 )
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#define DSI0_HS_CLT0_MASK 0xfffffffc
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#define DSI0_HS_CLT0_WIDTH 32
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#define DSI0_HS_CLT0_RESET 0000000000
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#define DSI0_HS_CLT1 HW_REGISTER_RW( 0x7e209048 )
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#define DSI0_HS_CLT1_MASK 0x000003fc
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#define DSI0_HS_CLT1_WIDTH 10
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#define DSI0_HS_CLT1_RESET 0000000000
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#define DSI0_HS_CLT2 HW_REGISTER_RW( 0x7e20904c )
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#define DSI0_HS_CLT2_MASK 0x000003fc
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#define DSI0_HS_CLT2_WIDTH 10
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#define DSI0_HS_CLT2_RESET 0000000000
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#define DSI0_HS_DLT3 HW_REGISTER_RW( 0x7e209050 )
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#define DSI0_HS_DLT3_MASK 0x000003fc
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#define DSI0_HS_DLT3_WIDTH 10
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#define DSI0_HS_DLT3_RESET 0000000000
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#define DSI0_HS_DLT4 HW_REGISTER_RW( 0x7e209054 )
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#define DSI0_HS_DLT4_MASK 0x000003fc
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#define DSI0_HS_DLT4_WIDTH 10
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#define DSI0_HS_DLT4_RESET 0000000000
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#define DSI0_HS_DLT5 HW_REGISTER_RW( 0x7e209058 )
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#define DSI0_HS_DLT5_MASK 0x000003fc
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#define DSI0_HS_DLT5_WIDTH 10
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#define DSI0_HS_DLT5_RESET 0000000000
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#define DSI0_LP_DLT6 HW_REGISTER_RW( 0x7e20905c )
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#define DSI0_LP_DLT6_MASK 0x000003fc
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#define DSI0_LP_DLT6_WIDTH 10
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#define DSI0_LP_DLT6_RESET 0000000000
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#define DSI0_LP_DLT7 HW_REGISTER_RW( 0x7e209060 )
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#define DSI0_LP_DLT7_MASK 0x000003fc
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#define DSI0_LP_DLT7_WIDTH 10
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#define DSI0_LP_DLT7_RESET 0000000000
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#define DSI0_PHY_AFEC0 HW_REGISTER_RW( 0x7e209064 )
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#define DSI0_PHY_AFEC0_MASK 0x000000ff
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#define DSI0_PHY_AFEC0_WIDTH 8
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#define DSI0_PHY_AFEC0_RESET 0000000000
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#define DSI0_PHY_AFEC1 HW_REGISTER_RW( 0x7e209068 )
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#define DSI0_PHY_AFEC1_MASK 0xffffffff
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#define DSI0_PHY_AFEC1_WIDTH 32
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#define DSI0_PHY_AFEC1_RESET 0000000000
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#define DSI0_TST_SEL HW_REGISTER_RW( 0x7e20906c )
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#define DSI0_TST_SEL_MASK 0x000000ff
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#define DSI0_TST_SEL_WIDTH 8
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#define DSI0_TST_SEL_RESET 0000000000
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#define DSI0_TST_MON HW_REGISTER_RW( 0x7e209070 )
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#define DSI0_TST_MON_MASK 0x000000ff
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#define DSI0_TST_MON_WIDTH 8
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#define DSI0_TST_MON_RESET 0000000000
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