Wolfgang Spraul
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0ebac7068f
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finished gclk
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2012-08-01 04:28:43 +02:00 |
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Wolfgang Spraul
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17857de4d2
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moving functions around a little
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2012-07-31 11:24:30 +02:00 |
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Wolfgang Spraul
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76e644bb52
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cleanup, fixes, some gclk vertical wiring
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2012-07-31 08:53:07 +02:00 |
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Wolfgang Spraul
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60d8370497
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added small text utilities hstrrep, sort_seq and merge_seq
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2012-07-30 09:11:56 +02:00 |
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Wolfgang Spraul
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3f7db4d968
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more powerful hashed string array, high-speed search and replace utility
hstrrep
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2012-07-29 05:59:59 +02:00 |
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Wolfgang Spraul
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f2f5e5e027
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working
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2012-07-28 13:53:13 +02:00 |
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Wolfgang Spraul
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f2a2c5d2b7
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wires left and right
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2012-07-28 07:42:31 +02:00 |
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Wolfgang Spraul
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1dadb4c381
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started with global clock wiring
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2012-07-27 16:01:34 +02:00 |
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Wolfgang Spraul
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904108d50a
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finished tile positioning cleanup
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2012-07-27 09:10:09 +02:00 |
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Wolfgang Spraul
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3b9fa11659
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tile positioning cleanup p1
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2012-07-27 07:45:26 +02:00 |
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Wolfgang Spraul
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f7ada88c59
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some dcm and pll wiring
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2012-07-27 03:31:30 +02:00 |
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Wolfgang Spraul
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c768c507a7
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small sort order fix
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2012-07-26 13:55:59 +02:00 |
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Wolfgang Spraul
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ae2438cca0
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cleanup, wires, new_fp prints static connections
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2012-07-26 05:26:27 +02:00 |
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Wolfgang Spraul
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9ecc9d7475
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first steps in logic wires
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2012-07-25 14:01:24 +02:00 |
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Wolfgang Spraul
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fd7236242e
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wires
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2012-07-25 11:24:42 +02:00 |
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Wolfgang Spraul
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c5098634c4
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wires
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2012-07-25 10:03:25 +02:00 |
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Wolfgang Spraul
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7266c64eca
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modeling
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2012-07-25 08:00:19 +02:00 |
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Wolfgang Spraul
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f8d1911cd2
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wires 1.1%
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2012-07-25 04:58:40 +02:00 |
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Wolfgang Spraul
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c9718d0372
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wires
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2012-07-25 03:03:23 +02:00 |
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Wolfgang Spraul
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44cd3b0b7f
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wires
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2012-07-24 15:38:01 +02:00 |
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Wolfgang Spraul
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7f74817e78
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modeling wires, about 0.7% of them done
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2012-07-24 05:49:14 +02:00 |
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Wolfgang Spraul
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325c31920b
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another small wire segment modeled
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2012-07-24 03:57:11 +02:00 |
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Wolfgang Spraul
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00b29604e0
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minor README update
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2012-07-23 10:40:09 +02:00 |
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Wolfgang Spraul
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a17588fac5
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modeled first line - NN2
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2012-07-23 10:34:28 +02:00 |
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Wolfgang Spraul
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b4ad7801b0
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minor model cleanup
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2012-07-21 06:04:08 +02:00 |
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Wolfgang Spraul
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970eb4eee9
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added simple hashed string array for tile and wire names
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2012-07-19 17:29:25 +02:00 |
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Wolfgang Spraul
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40cb5e88a0
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added new stub util new_floorplan
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2012-07-18 04:37:15 +02:00 |
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Wolfgang Spraul
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d1e8d5f557
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moved model into separate file so multiple utils can use it
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2012-07-17 10:58:07 +02:00 |
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Wolfgang Spraul
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9d0a00856b
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finished first round in tile modeling - next back to semiconductor
devices and routing
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2012-07-15 18:11:28 +02:00 |
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Wolfgang Spraul
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f69912f094
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started modeling left side of chip
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2012-07-15 09:09:14 +02:00 |
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Wolfgang Spraul
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2bdbea85fb
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finished top, bottom and center - left and right missing
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2012-07-13 13:24:10 +00:00 |
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Wolfgang Spraul
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f99572195a
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working on C model
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2012-07-13 01:35:27 +00:00 |
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Wolfgang Spraul
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1582b4833c
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ran into a wall with routing drawings, starting a C model of the chip
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2012-07-11 16:01:01 +02:00 |
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Wolfgang Spraul
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aedf4bd4b4
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a little DSP support, lots of reading and thinking
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2012-07-08 03:47:59 +02:00 |
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Wolfgang Spraul
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492a8bbae4
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minor lut fix
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2012-07-01 07:49:52 +02:00 |
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Wolfgang Spraul
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9539c70fb6
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initial lut support
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2012-06-29 08:07:38 +02:00 |
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Wolfgang Spraul
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09be589957
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finished frame cleanup. tomorrow: back to clb, then other primitives.
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2012-06-28 16:06:28 +02:00 |
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Wolfgang Spraul
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42af03e705
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minor cleanup, bug fixes
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2012-06-28 06:04:42 +02:00 |
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Wolfgang Spraul
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80459797ed
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committing a bit more frequently because my HDD clicks strangely and
replacement only arrives tomorrow...
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2012-06-27 09:28:24 +02:00 |
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Wolfgang Spraul
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8a0bff748d
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incremental commit, some refactoring
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2012-06-27 04:07:54 +02:00 |
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Wolfgang Spraul
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76a6d6a9e2
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little more ramb16 cleanup. next: two-pass frame handling, better
support for compressed bitstreams
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2012-06-26 08:51:09 +02:00 |
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Wolfgang Spraul
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5588961fd2
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cleaner ramb16 inst
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2012-06-26 04:55:03 +02:00 |
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Wolfgang Spraul
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bc12dd96f3
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ramb16 cleanup, going public domain, see unlicense.org
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2012-06-26 01:45:43 +02:00 |
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Wolfgang Spraul
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41f376de33
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added quine-mccluskey algo, still open: petrick's method, xor, others?
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2012-06-24 06:57:37 +02:00 |
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Wolfgang Spraul
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687e706c16
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css
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2012-06-23 16:55:17 +02:00 |
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Wolfgang Spraul
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0f1d1a704d
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finished lut equiv. schematic
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2012-06-23 16:54:53 +02:00 |
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Wolfgang Spraul
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427fc81e38
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added some boolean algebra (part I)
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2012-06-23 00:55:54 +02:00 |
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Wolfgang Spraul
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79b404dcf9
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shorten the output a little, make it more readable
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2012-06-20 04:25:49 +02:00 |
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Wolfgang Spraul
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3f98db058e
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tiny svg steps
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2012-06-18 04:47:51 +02:00 |
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Wolfgang Spraul
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691e0427d1
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learned a little about the I/O pins
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2012-06-17 15:29:39 +02:00 |
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